US3648275A
Expired / Lapsed
US
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Buffered analog converter
Assignee: National Aeronautics and Space Administration
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Filing: 1970-04-03
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Granted: 1972-03-07
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Expires: 1990-04-03
Abstract
Abstract A converter for converting a binary digital code into an analog representation. The converter includes a timing system which is operated by a clock signal to produce a synchronized timing pulse. The digital information is fed into a holding register, and such is gated through a plurality of gates that feeds the complement of the digital code into a counter. The relative duration of the output signal of the last state of the counter in a logic ''''one'''' state corresponds to the weight of the digital code being fed into the holding register.
Inventors
- 👤 Kenneth F Bower
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 06:38
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/66; H03M1/82
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
378 words
A converter for converting a P-bit binary code in which each bit of said code is either a logic ''''0'''' or a logic ''''1'''' to an analog representation comprising: A. a holding register having inputs and parallel outputs, B. means for gating said binary code into said holding register, C. a plurality of gates corresponding in number to said bits of information in said code, D. an activating gate having an output, E. said plurality of gates having parallel outputs and parallel inputs coupled to the parallel outputs of said holding register, F. a binary counter having a plurality of stages corresponding in number to said bits of information plus a last stage, all being connected in series, G. said plurality of stages of said binary counter having parallel inputs coupled to corresponding outputs of said plurality of gates, H. said last stage of said binary counter having an input coupled to said output of said activating gate, I. means for activating said plurality of gates and said activating gate for shifting said binary code in complementary form from said holding register into corresponding stages of said binary counter and causing said last stage of said binary counter to be set to the ''''1'''' state, J. a NAND gate having a pair of inputs and an output, K. means for coupling the output of said NAND gate to a first stage of said binary counter, L. means for applying a repeating clock signal to one of said inputs of said NAND gate for causing said counter to count in sequence according to the binary code stored in said binary counter so that the duration that said last stage of said binary counter remains in said ''''1'''' state corresponds to the value of said binary code, M. means for coupling the output of said last stage of said binary counter to an input of said NAND gate for interrupting said clock signal being supplied to said first stage of said binary counter responsive to said last stage of said binary counter changing back to its original state, and N. filter means coupled to the output of said last stage of said binary counter for producing a DC signal having an amplitude corresponding to the value of said binary code.
Claim 2
Dependent Claim
378 words
A converter for converting a P-bit binary code in which each bit of said code is either a logic ''''0'''' or a logic ''''1'''' to an analog representation comprising: A. a holding register having inputs and parallel outputs, B. means for gating said binary code into said holding register, C. a plurality of gates corresponding in number to said bits of information in said code, D. an activating gate having an output, E. said plurality of gates having parallel outputs and parallel inputs coupled to the parallel outputs of said holding register, F. a binary counter having a plurality of stages corresponding in number to said bits of information plus a last stage, all being connected in series, G. said plurality of stages of said binary counter having parallel inputs coupled to corresponding outputs of said plurality of gates, H. said last stage of said binary counter having an input coupled to said output of said activating gate, I. means for activating said plurality of gates and said activating gate for shifting said binary code in complementary form from said holding register into corresponding stages of said binary counter and causing said last stage of said binary counter to be set to the ''''1'''' state, J. a NAND gate having a pair of inputs and an output, K. means for coupling the output of said NAND gate to a first stage of said binary counter, L. means for applying a repeating clock signal to one of said inputs of said NAND gate for causing said counter to count in sequence according to the binary code stored in said binary counter so that the duration that said last stage of said binary counter remains in said ''''1'''' state corresponds to the value of said binary code, M. means for coupling the output of said last stage of said binary counter to an input of said NAND gate for interrupting said clock signal being supplied to said first stage of said binary counter responsive to said last stage of said binary counter changing back to its original state, and N. filter means coupled to the output of said last stage of said binary counter for producing a DC signal having an amplitude corresponding to the value of said binary code.
Claim 3
Dependent Claim
57 words
The converter as set forth in claim 1 wherein: A. said means for activating said activating gate is synchronized with said clock signal so that said plurality of gates and said activating gate are activated only once during a period of time necessary for the binary counter to count from the first stage to said last stage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-03-07 | 1975-09-06 | 1976-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-03-07 | 1979-09-06 | 1980-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-03-07 | 1983-09-06 | 1984-03-07 | $7700.00 | Window Closed / Lapsed |