Programmable timing system

Claim 1

A timing system comprising: a clock for generating clock signals; first counting means connected to receive and count said clock signals for providing first output signals at predetermined counts, comprising a first set of logic gates each clocked by said clock signals and wherein a modulus of said first counting means corresponds to which gates are enabled; means connected to said first counting means for varying the modulus of said first counting means comprising, a second set of logic gates, each gate in said second set being coupled to an enabling input of one of said first set of logic gates, wherein each gate in said second set is enabled by one or more modulus select signals so that said first output signals are delayed by a number of clock signal counts equal to a selected modulus; second counting means connected to receive said first output signals for counting said first output signals and providing second output signals at predetermined counts; and at least one programmable delay means each connected to the outputs of said first and second counting means for providing a timing signal of a preselected duration upon the occurrence of each of said first and second output signals.