US4310801A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable divider
Assignee: Stewart Warner Alemite and Instrument Corp
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Filing: 1979-05-16
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Granted: 1982-01-12
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Expires: 1999-05-16
Abstract
Abstract A programmable divider is provided for dividing the frequency of an input signal by a selectable integer. The divider includes a multiple stage ripple counter, a transmission gate coupled between each stage of the ripple counter and a means for producing an output signal, and a means for selectively enabling each transmission gate.
Inventors
- 👤 John D. Baker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:53
CPC Classifications
G; G01; G01P; G01P21/00; G01P21/02; G01C; G01C22/00; G01C22/02; H; H03; H03K; H03K23/00; H03K23/64; H03K23/66
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
149 words
A divider for dividing the frequency of an input signal by a selectable integer to produce an output signal comprising: (a) a multiple stage ripple counter incremented by said input signal and having an output for each stage thereof, (b) means selectively enabled to gate the output of each stage of said counter to a producing means, said gating means comprising a separate transmission gate coupled between the output of each stage and the producing means for transmitting, when enabled, the output of each stage to the producing means independent of the state of the output of any stage, (c) means for enabling selected ones of said transmission gates, the value of said integer being determined by selecting which of said transmission gates are enabled, (d) means for producing said output signal only when an output is received from all counter stages whose corresponding gating means have been enabled.
Claim 2
Dependent Claim
149 words
A divider for dividing the frequency of an input signal by a selectable integer to produce an output signal comprising: (a) a multiple stage ripple counter incremented by said input signal and having an output for each stage thereof, (b) means selectively enabled to gate the output of each stage of said counter to a producing means, said gating means comprising a separate transmission gate coupled between the output of each stage and the producing means for transmitting, when enabled, the output of each stage to the producing means independent of the state of the output of any stage, (c) means for enabling selected ones of said transmission gates, the value of said integer being determined by selecting which of said transmission gates are enabled, (d) means for producing said output signal only when an output is received from all counter stages whose corresponding gating means have been enabled.
Claim 3
Dependent Claim
42 words
The divider circuit according to claim 1 further including a one shot multivibrator receiving said output signal and producing a further signal, the duration of which is a function of the values of the timing resistor and capacitor associated with said multivibrator.
Claim 4
Dependent Claim
16 words
The divider circuit according to claim 1 wherein said ripple counter has at least eight stages.
Claim 5
Dependent Claim
17 words
The divider circuit according to claim 1 wherein said counter is an eight stage binary ripple counter.
Claim 6
Dependent Claim
25 words
The divider circuit according to claim 1 further including means for resetting said counter each time an output signal is produced by said producing means.
Claim 7
Dependent Claim
45 words
The divider circuit according to claim 1 wherein said enabling means includes: (a) a program input terminal for each gating means, (b) means for connecting each of said program input terminals to one of two voltage levels, one of said levels enabling said gating means.
Claim 8
Dependent Claim
70 words
The divider circuit according to claim 1 wherein said enabling means includes: (a) a program input terminal for each of said transmission gates, (b) means for detecting the voltage level applied to each of said terminals and for operating the control lines of said transmission gates if a first voltage level is present at said input terminals and inhibiting said switch control lines if a second voltage level is present.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-01-11 | 1985-07-13 | 1986-01-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-01-11 | 1989-07-13 | 1990-01-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-01-11 | 1993-07-13 | 1994-01-12 | $7700.00 | Window Closed / Lapsed |