External condition responsive circuit producing alarm when frequency (engine speed) to amplitude signal (oil pressure) ratio exceeds threshold

Claim 2

A switching circuit comprising first and second input terminals for receiving respective digital and analog electrical input signals, an output terminal for deriving an alarm output signal from said circuit, a digital counter coupled to said first input terminal, an analog time delay coupled to said second input terminal, said analog time delay being coupled to said digital counter to modify the count of said counter in accordance with the magnitude of an electrical analog signal at said second input, and means coupling said digital counter to said output terminal for producing an alarm signal at said output terminal when the count in said counter exceeds a predetermined value.

Claim 3

A circuit according to claim 1 wherein said counter comprises a binary counter.

Claim 4

A circuit according to claim 1 wherein said analog time delay circuit is coupled to said counter to vary the counting time of said counter.

Claim 5

A circuit according to claim 3 wherein said counter comprises a resettable counter.

Claim 6

A circuit according to claim 4 wherein said counter has a reset terminal, said analog time delay circuit being coupled to said reset terminal of said counter.

Claim 7

A switching circuit comprising first and second input terminals for receiving respective digital and analog electrical input signals, an output terminal for deriving an alarm output signal from said circuit, a digital counter coupled to said first input terminal, an analog time delay coupled to said second input terminal, said analog time delay being coupled to said digital counter to modify the count of said counter in accordance with the magnitude of an electrical analog signal at said second input, means coupling said digital counter to said output terminal for producing an alarm signal at said output terminal when the count in said counter exceeds a predetermined value, said analog time delay circuit being coupled to said counter to vary the counting time of said counter, said counter comprising a resettable counter, said counter having a reset terminal, said analog time delay circuit being coupled to said reset terminal of said counter, and wherein said analog time delay circuit comprises a one-shot multivibrator.

Claim 8

A switching circuit comprising first and second input terminals for receiving respective digital and analog electrical input signals, an output terminal for deriving an alarm output signal from said circuit, a digital counter coupled to said first input terminal, an analog time delay coupled to said second input terminal, said analog time delay being coupled to said digital counter to modify the count of said counter in accordance with the magnitude of an electrical analog signal at said second input, means coupling said digital counter to said output terminal for producing an alarm signal at said output terminal when the count in said counter exceeds a predetermined value, said analog time delay circuit being coupled to said counter to vary the counting time of said counter, said counter comprising a resettable counter, said counter having a reset terminal, said analog time delay circuit being coupled to said reset terminal of said counter, and wherein said analog time delay circuit comprises a one-shot multivibrator.

Claim 9

A circuit according to claim 6 wherein said analog time delay circuit comprises a capacitor which acts as a timing element for said multivibrator, and means coupling said second input terminal to said capacitor.

Claim 10

A circuit according to claim 7 wherein said means coupling said second input terminal to said capacitor comprises a voltage to current converter.

Claim 11

A switching circuit comprising first and second input terminals for receiving respective digital and analog electrical input signals, an output terminal for deriving an alarm output signal from said circuit, a counter having a reset terminal for controlling the length of the counting cycle of said counter, an analog time delay coupled to said counter reset terminal for varying the counting cycle of said timer in accordance with the period of said delay, and means coupling said analog time delay to said second input terminal.

Claim 12

A switching circuit comprising first and second input terminals for receiving respective digital and analog electrical input signals, an output terminal for deriving an alarm output signal from said circuit, a counter having a reset terminal for controlling the length of the counting cycle of said counter, an analog time delay coupled to said counter reset terminal for varying the counting cycle of said timer in accordance with the period of said delay, and means coupling said analog time delay to said second input terminal.

Claim 13

A switching circuit according to claim 9 wherein said means coupling said analog time delay to said second input terminal comprises a voltage to current converter.

Claim 14

A switching circuit comprising first and second input terminals for receiving respective digital and analog electrical input signals, an output terminal for deriving an alarm output signal from said circuit, a counter having a reset terminal for controlling the length of the counting cycle of said counter, an analog time delay coupled to said counter reset terminal for varying the counting cycle of said timer in accordance with the period of said delay, and means coupling said analog time delay to said second input terminal, said means coupling said analog time delay to said second input terminal comprising a voltage to current converter, said analog time delay comprising a one-shot multivibrator having a timing capacitor, said voltage to current converter being coupled to said capacitor.

Claim 15

A switching circuit comprising first and second input terminals for receiving respective digital and analog electrical input signals, an output terminal for deriving an alarm output signal from said circuit, a counter having a reset terminal for controlling the length of the counting cycle of said counter, an analog time delay coupled to said counter reset terminal for varying the counting cycle of said timer in accordance with the period of said delay, and means coupling said analog time delay to said second input terminal, said means coupling said analog time delay to said second input terminal comprising a voltage to current converter, said analog time delay comprising a one-shot multivibrator having a timing capacitor, said voltage to current converter being coupled to said capacitor.

Claim 16

A switching circuit according to claim 11 wherein said counter comprises a plurality of binary stages, said one-shot multivibrator being coupled to the first stage of said counter.

Claim 17

A switching circuit according to claim 12 wherein said one-shot multivibrator has its input coupled to said first stage of said counter, and means coupling the output of said multivibrator to said reset terminal of said counter.

Claim 18

A switching circuit according to claim 13 including a time delay circuit coupled between the output and the input of said one-shot multivibrator.

Claim 19

A switching circuit according to claim 14 including a NAND gate having its output coupled to the input of said one-shot multivibrator, a first input of said NAND gate being coupled to the first stage of said counter and a second input of said NAND gate being coupled to the output of said time delay circuit.

Claim 20

A switching circuit according to claim 15 wherein said means coupling the output of said multivibrator to said reset terminal of said counter comprises a second one-shot multivibrator.

Claim 21

A switching circuit according to claim 16 including a relay coupled to said output terminal.

Claim 22

A switching circuit according to claim 17 including a reset flip-flop coupling the last stage of said counter to said output terminal, and a manual reset switch coupled to said flip-flop.

Claim 23

A switching circuit according to claim 16 wherein said voltage-to-current converter comprises a junction transistor having its emitter-collector circuit coupled to said timing capacitor of said one-shot multivibrator.

Claim 24

A switching circuit according to claim 19 including a differential amplifier coupling said second input terminal to the base of said junction transistor.