Digital frequency synthesizer for generating a frequency-modulated signal and radio frequency apparatus including such a device

Claim 2

Digital frequency synthesizer apparatus for generating a frequency modulated output signal S, comprising: clock means for providing a clock signal having a frequency f H and a period T=1/f H ; programmable divider means, connected to said clock means, for receiving said clock signal and generating a pulse signal R which has a variable cycle equal to NT (where N is a whole integer which can take any value from 0 to n) and a pulse width equal to T; shaping means, connected to said programmable divider means, for receiving said pulse signal R and producing said output signal S which has a half-cycle corresponding to said pulse signal cycle; and control means, connected to said programmable divider means and to said shaping means and adapted to receive a control signal S d , for successively supplying the values of N to said programmable divider means in accordance with said control signal S d so that said output signal S is frequency modulated according to a sequence of values of N.

Claim 3

Apparatus according to claim 1 wherein said programmable divider means includes a decrementing counter which is set to N at the beginning of said pulse signal cycle and decreases, by a whole integer during each clock cycle, to 0 whereupon the next successive value of N is supplied to said decrementing counter from said control means.

Claim 4

Apparatus according to claim 1 wherein said programmable divider means includes a programmable counter which is set to N M +1-N (where N M equals the maximum count of said programmable counter) at the beginning of said pulse signal cycle and increases, by a whole integer during each clock cycle, to N M whereupon the next successive value of N is supplied to said programmable counter from said control means.

Claim 5

Apparatus according to claim 1 wherein said shaping means includes a divide-by-two circuit which supplies said output signal S having half-cycles equal to NT where the value of N varies as commanded by said control signal S d .

Claim 6

Apparatus according to claim 1 wherein said control means includes: address counting means for successively generating one of a plurality of address gianls each time said pulse signal cycle is complete; memory means, connected to said address counting means, for storing said values of N, and for supplying successive values of N to said programmable divider means in accordance with said address signals, and for generating an end-of-sequence signal S f when all of the values of N for a sequence have been supplied to said programmable divider means; and flip-flop means, connected to said address counting means and said memory means and adapted to receive said control signal S d , for generating an initialization signal S RAZ which initializes said programmable divider means and said shaping means and resets said address counting means upon receipt of said control signal S d or said end-of-sequence signal S F .

Claim 7

Apparatus according to claim 5 wherein said memory means includes a read-only-memory in which each of said values of N is assigned a unique address, with the address A N , which contains a last one of said sequence of values of N, also including a first and second bit corresponding to said end-of-sequence signal S f and a control signal S m , respectively.

Claim 8

Apparatus according to claim 5 wherein said memory means includes: counter means for supplying said successive valueS of N to said programmable divider means, said counter means storing said values of N in a predetermined sequence beginning with an initial value N o , whereby said initial value N o is supplied upon receipt of said initialization signal S RAZ and successive values of N are supplied by incrementing or decrementing or holding the count of said counter means constant in accordance with the receipt of command bits a and b; read-only-memory means for receiving said address signals from said address counting means and generating said command bits a and b in accordance with said address signals, and for combining each of said bits a and b with said pulse signal R so as to provide said bits a and b to said counter means once during each pulse signal cycle, and for generating said end-of-sequence signal S f .

Claim 9

Apparatus according to claim 7 wherein said counter means supplies a control signal S m which is formed by a least significant bit from each of said successive values of N supplied to said programmable divider means.

Claim 10

Apparatus according to claim 1 further comprising supplementary circuit means, connected to said shaping means, for receiving said output signal S and generating a phase precise output signal S' whereby said apparatus may be used with a low clock frequency, said supplementary circuit comprising: delay means, having M outputs and receiving said clock frequency f H and said output signal S, for delaying said output signal S and providing delayed signals S 1 . . . S M at said M outputs, respectively, each of said delayed signals being delayed by a period equal to jT/(M+1) (where j=the sequential number of said outputs 1 to M); and multiplexing means, connected to said delay means and receiving a control signal S M from said control means, for selecting at each pulse signal cycle one of said delayed signals S 1 . . . S M in accordance with said control signal S M to produce said phase precise output signal S'.

Claim 11

Apparatus according to claim 9 wherein said delay means includes two type D flip-flops, one operating on a rising front of said clock signal and the other operating on a falling front of said clock signal.

Claim 12

Apparatus according to claim 9 wherein said delay means includes a delay line having M outputs.

Claim 13

Apparatus according to claim 1 further comprising supplementary circuit means, connected to said programmable divider means for receiving said pulse signal R and generating a phase precise pulse signal R' whereby said apparatus may be used with a low clock frequency, said supplementary circuit comprising: delay means, having M outputs and receiving said clock frequency f H and said pulse signal R, for delaying said pulse signal R and providing delayed signals R 1 . . . R M at said M outputs, respectively, each of said delayed signals being delayed by a period equal to jT/(M+1) (where j=the sequential number of said outputs 1 to M); and multiplexing means, connected to said delay means and receiving a control signal S M from said control means, for selecting at each pulse signal cycle one of said delayed signals R 1 . . . R M in accordance with said control signal S M to produce said phase precise pulse signal R'.

Claim 14

Apparatus according to claim 9 wherein said multiplexing means includes a multiplexer having (M+1) inputs and one output.

Claim 15

Radio-frequency apparatus for providing a phase precise, digitally-generated, frequency-modulated signal Sμ, comprising: digital frequency synthesizer apparatus for generating a frequency modulated output signal S, including: clock means for providing a clock signal having a frequency f H and a period T=1/f H ; programmable divider means, connected to said clock means, for receiving said clock signal and generating a pulse signal R which has a variable cycle equal to NT (where N is a whole integer varying between 0 and n) and a pulse width equal to T; shaping means, connected to said programmable divider means, for receiving said pulse signal R and producing said output signal S which has a half-cycle corresponding to said pulse signal cycle; and control means, connected to said programmable divider means and to said shaping means and adapted to receive a control signal S d , for successively supplying the values of N to said programmable divider means in accordance with said control signal S d so that said output signal S is frequency modulated according to a sequence of values of N; a first oscillator providing a signal of fixed frequency F 1 ; a second oscillator providing said signal Sμ having a controllable frequency F 2 ; mixer means, connected to said first and second oscillators, for mixing said fixed frequency and said controllable frequency signals and providing a mixed signal of frequency (F 2 -F 1 ); low pass filter means for receiving said mixed signal and providing a filtered, mixed signal; divide-by-X circuit means for dividing said filtered, mixed signal and providing a divided signal of frequency (F 2 -F 1 )/X; phase comparator means, connected to said divide-by-X circuit means and said digital frequency synthesizer apparatus, for comparing the phase of said output signal S and said divided signal and providing a compared signal; and control circuit means for receiving said compared signal from said phase comparator means and supplying a controlling signal to said second oscillator for controlling the frequency of said useful signal Sμ.

Claim 16

Radio-frequency apparatus for providing a phase precise, digitally-generated, frequency-modulated signal Sμ, comprising: digital frequency synthesizer apparatus for generating a frequency modulated output signal S, including: clock means for providing a clock signal having a frequency f H and a period T=1/f H ; programmable divider means, connected to said clock means, for receiving said clock signal and generating a pulse signal R which has a variable cycle equal to NT (where N is a whole integer varying between 0 and n) and a pulse width equal to T; shaping means, connected to said programmable divider means, for receiving said pulse signal R and producing said output signal S which has a half-cycle corresponding to said pulse signal cycle; and control means, connected to said programmable divider means and to said shaping means and adapted to receive a control signal S d , for successively supplying the values of N to said programmable divider means in accordance with said control signal S d so that said output signal S is frequency modulated according to a sequence of values of N; a first oscillator providing a signal of fixed frequency F 1 ; a second oscillator providing said signal Sμ having a controllable frequency F 2 ; mixer means, connected to said first and second oscillators, for mixing said fixed frequency and said controllable frequency signals and providing a mixed signal of frequency (F 2 -F 1 ); low pass filter means for receiving said mixed signal and providing a filtered, mixed signal; divide-by-X circuit means for dividing said filtered, mixed signal and providing a divided signal of frequency (F 2 -F 1 )/X; phase comparator means, connected to said divide-by-X circuit means and said digital frequency synthesizer apparatus, for comparing the phase of said output signal S and said divided signal and providing a compared signal; and control circuit means for receiving said compared signal from said phase comparator means and supplying a controlling signal to said second oscillator for controlling the frequency of said useful signal Sμ.

Claim 17

Apparatus according to claim 14 wherein said phase comparator means includes a frequency phase comparator operating on rising or falling fronts, and wherein said digital frequency synthesizer apparatus provides an output signal which has a cycle equal to said pulse signal cycle.