US4559608A — Arithmetic logic unit

Claim 1

Independent Claim 169 words

In an arithmetic logic unit having a first section for producing a propagate and a generate output signals from a pair of input variables per bit and logic select signals provided thereto, and a second section for producing a carry and a sum output signal from said propagate and generate signals, the improvement comprising: first precharge means in said first section for precharging the propagate and generate output signal to a first logic level in response to precharge signals; first latch means integral with said arithmetic logic unit and responsive to a transition of said propagate output signal from said first logic level to a second logic level for maintaining said propagate signal at said second logic level until the next precharge signal; and second latch means integral with said arithmetic logic unit and responsive to a transition of said generate output signal from said first logic level to a second logic level for maintaining said generate output signal at said second logic level until the next precharge signal.

Claim 2

Dependent Claim 169 words

In an arithmetic logic unit having a first section for producing a propagate and a generate output signals from a pair of input variables per bit and logic select signals provided thereto, and a second section for producing a carry and a sum output signal from said propagate and generate signals, the improvement comprising: first precharge means in said first section for precharging the propagate and generate output signal to a first logic level in response to precharge signals; first latch means integral with said arithmetic logic unit and responsive to a transition of said propagate output signal from said first logic level to a second logic level for maintaining said propagate signal at said second logic level until the next precharge signal; and second latch means integral with said arithmetic logic unit and responsive to a transition of said generate output signal from said first logic level to a second logic level for maintaining said generate output signal at said second logic level until the next precharge signal.

Claim 3

Dependent Claim 85 words

The arithmetic logic unit according to claim 1 wherein said first and second latch means each include a first and second switch means, connected in series between the output terminal for said propagate or generate output signal and a source of second logic level signal, for latching said output terminal at said second logic level when both the switch means are activated, said first switch is activated by said first to second logic level transition, said second switch means is deactivated by said precharge signal.

Claim 4

Dependent Claim 36 words

The arithmetic logic unit according to claim 1 wherein one of said inputs is a bidirectional bus through said arithmetic logic unit and including means for writing onto said bidirectional bus from said arithmetic logic unit.

Claim 5

Dependent Claim 44 words

The arithmetic logic unit according to claim 3 including means connected to said first section for isolating said propagate and generate output signals and said first and second latch means from said inputs during a write from said arithmetic logic unit onto said bus.

Claim 6

Dependent Claim 55 words

The arithmetic logic unit according to claim 4 wherein said first section includes means for determining the arithmetic or logic operation used on said input variables to produce propagate and generate signals in response to said logic select signals and said isolation means includes said determining means which is totally deselected to perform said isolation.

Claim 7

Dependent Claim 147 words

In an arithmetic logic unit having a first section for producing the product terms of the true and complement of a pair of input variables per bit, a second section connected to said first section for producing a propagate and a generate output signals using product terms selected by logic select signals, and a third section for producing a carry and sum output signal from said propagate and generate signals, the improvement: means for providing logic high and lows of said true and complement of said pair of input variables per bit after a precharge cycle and logic high for both said true and complements during said precharge; and said first section includes for each bit a plurality of pairs of serial connected P channel field effect transistors each having their gate connected to an appropriate true or complement input variable to perform a NOR logic function.

Claim 8

Dependent Claim 147 words

In an arithmetic logic unit having a first section for producing the product terms of the true and complement of a pair of input variables per bit, a second section connected to said first section for producing a propagate and a generate output signals using product terms selected by logic select signals, and a third section for producing a carry and sum output signal from said propagate and generate signals, the improvement: means for providing logic high and lows of said true and complement of said pair of input variables per bit after a precharge cycle and logic high for both said true and complements during said precharge; and said first section includes for each bit a plurality of pairs of serial connected P channel field effect transistors each having their gate connected to an appropriate true or complement input variable to perform a NOR logic function.

Claim 9

Dependent Claim 34 words

The arithmetic logic unit according to claim 6, wherein said second section includes propagate latch means and generate latch means connected to the propagate and generate outputs and means to precharge said latch means.

Claim 10

Dependent Claim 27 words

The arithmetic logic unit according to claim 6 including a precharge means for precharging the drain of each of said P channel field effect transistors logic low.

Claim 11

Dependent Claim 113 words

In an arithmetic logic unit for performing binary coded decimal arithmetic of a plurality of bits having a carry and sum logic section and an output section for shifting right or left and swapping upper and lower bytes of the sum outputs of said carry and sum logic section, the improvement comprising said carry and sum logic being grouped by nibbles of four bits, the carry and sum logic of a first and second nibble being separated by the carry and sum logic of a third nibble and the carry and sum logic of said third nibble and a fourth nibble being separated by the carry and sum logic of said second nibble.

Claim 12

Dependent Claim 113 words

In an arithmetic logic unit for performing binary coded decimal arithmetic of a plurality of bits having a carry and sum logic section and an output section for shifting right or left and swapping upper and lower bytes of the sum outputs of said carry and sum logic section, the improvement comprising said carry and sum logic being grouped by nibbles of four bits, the carry and sum logic of a first and second nibble being separated by the carry and sum logic of a third nibble and the carry and sum logic of said third nibble and a fourth nibble being separated by the carry and sum logic of said second nibble.

Claim 13

Dependent Claim 154 words

In a carry and sum logic unit for a plurality of bits including for each bit a carry means for producing a carry-out signal as a function of a carry-in signal, a propagate signal and generate signal, and a sum means for producing a sum signal as a function of said carry-in signal and said propagate signal, the improvement comprising: said carry means of said first four bits being connected in series without carry look ahead, a carry-in to the first bit requires four logic delays to propagate to the output of the fourth bit carry means as a nibble carry; and said carry means of the fifth and subsequent bits being connected in series with carry look ahead means for a nibble of four bits, a carry-in to the first bit of the nibble requires one logic delay to propagate a nibble carry to the output of the fourth bit of the nibble.

Claim 14

Dependent Claim 154 words

In a carry and sum logic unit for a plurality of bits including for each bit a carry means for producing a carry-out signal as a function of a carry-in signal, a propagate signal and generate signal, and a sum means for producing a sum signal as a function of said carry-in signal and said propagate signal, the improvement comprising: said carry means of said first four bits being connected in series without carry look ahead, a carry-in to the first bit requires four logic delays to propagate to the output of the fourth bit carry means as a nibble carry; and said carry means of the fifth and subsequent bits being connected in series with carry look ahead means for a nibble of four bits, a carry-in to the first bit of the nibble requires one logic delay to propagate a nibble carry to the output of the fourth bit of the nibble.

Claim 15

Dependent Claim 88 words

The carry and sum logic unit according to claim 10 wherein said carry look ahead means includes first carry look ahead means for producing a nibble carry if all the propagate signals are logic high and if carry-in to the nibble is logic high, and second carry look ahead means for producing a nibble carry if a carry is generated by the second, third or fourth bit of the nibble and the carry is propagated by subsequent bits to the output of the fourth bit of the nibble.

Claim 16

Dependent Claim 47 words

The carry and sum logic unit according to claim 11 wherein said sum means for each bit includes an exclusive OR means having two inputs, one of said inputs is the propagate signal for that bit and the other input is the carry from the previous bit.

Claim 17

Dependent Claim 86 words

The carry and sum logic unit according to claim 12 wherein said sum means for the second, third and fourth bits each include carry means for providing said carry from the previous bit input to said exclusive OR means if a carry is generated by said second carry look ahead means for the previous bit or if said carry-in to the nibble is high and the propagate signals of the previous bits in the nibble are high as determined by said first carry look ahead means.

Claim 18

Dependent Claim 26 words

The carry and sum logic unit according to claim 10 including latch means at the output of each nibble for sampling and storing the nibble carryout.

Claim 19

Dependent Claim 161 words

A logic gate comprising: a first switch means having an input terminal connected to a first logic level source, an output terminal and a control terminal which is an input of said gate and controls the conduction between said input and output terminals of said first switch means; a second switch means having an input terminal connected to the output terminal of said first switch means, an output terminal which is the output of said gate, and a control terminal which is another input of said gate and controls the conduction between said input and output terminals of said second switch means; a first precharge means connected to said output terminal of said first switch means for precharging said output terminal of said first switch means to a second logic level; and a second precharge means connected to said output terminal of said second switch means for precharging said output terminal of said second switch means to said second logic level.

Claim 20

Dependent Claim 161 words

A logic gate comprising: a first switch means having an input terminal connected to a first logic level source, an output terminal and a control terminal which is an input of said gate and controls the conduction between said input and output terminals of said first switch means; a second switch means having an input terminal connected to the output terminal of said first switch means, an output terminal which is the output of said gate, and a control terminal which is another input of said gate and controls the conduction between said input and output terminals of said second switch means; a first precharge means connected to said output terminal of said first switch means for precharging said output terminal of said first switch means to a second logic level; and a second precharge means connected to said output terminal of said second switch means for precharging said output terminal of said second switch means to said second logic level.

Claim 21

Dependent Claim 47 words

A logic gate according to claim 15 including means connected to said output of said gate for maintaining said gate output at said second logic level after deactivation of said first and second precharge means except when both of said first and second switch means are conducting.

Claim 22

Dependent Claim 61 words

A logic gate according to claim 16 wherein said first and second switch means are transistors of a first conductivity type, said first precharge means includes a transistor of said first conductivity type, said second precharge means includes a transistor of a conductivity type opposite said first conductivity type, and said maintaining means includes a transistor of said second conductivity type.

Claim 23

Dependent Claim 53 words

A logic gate according to claim 16 wherein said first and second switch means are transistors of a first conductivity type, said first and second precharge means each include a transistor of a second conductivity type opposite said first conductivity type, and said maintaining means includes a transistor of said second conductivity type.

Claim 24

Dependent Claim 54 words

A logic gate according to claim 15 including a third switch means having an input terminal connected to said first logic level signal source, an output terminal connected to said gate output, and a control terminal which is a third input to said gate and controls the conduction between said input and output terminals.

Claim 25

Dependent Claim 51 words

A logic gate according to claim 19 wherein said first, second and third switch means are transistors of a first conductivity type, said first precharge means includes a transistor of said first conductivity type, and said second precharge means includes a transistor of a conductivity type opposite said first conductivity type.

Claim 26

Dependent Claim 42 words

A logic gate according to claim 19 wherein said first, second and third switch means are transistors of a first conductivity type, and said first and second precharge means each include a transistor of a conductivity type opposite said first conductivity type.

Claim 27

Dependent Claim 51 words

A logic gate according to claim 15 wherein said first and second switch means are transistors of a first conductivity type, said first precharge means includes a transistor of said first conductivity type, and said second precharge means includes a transistor of a second conductivity type opposite said first conductivity type.

Claim 28

Dependent Claim 40 words

A logic gate according to claim 15 wherein said first and second switch means are transistors of a first conductivity type, and said first and second precharge means are transistors of a second conductivity type opposite said first conductivity type.

Claim 29

Dependent Claim 26 words

A logic gate according to claim 15 wherein said first and second switches and said first and second precharge means are insulated gate field effect transistors.

Claim 30

Dependent Claim 68 words

The carry and sum logic unit according to claim 10, wherein each carry means and each sum means includes a precharge means connected to its output for precharging the output to a first logic level and a maintaining means connected to its output for maintaining said output at said first logic level after precharging until said carry means or sum means produces a carryout or sum signal respectively.

Claim 31

Dependent Claim 119 words

A logic gate comprising: a first switch means having an input terminal connected to a first logic level source, an output terminal which is the output of said gate and a control terminal which is an input of said gate and controls the conduction between said input and output terminals of said first switch means; a first precharge means connected to said output terminal of said first switch means for precharging said output terminal of said first switch means to a second logic level; and a maintaining means connected to said output of said gate for maintaining said gate output at said second logic level after deactivation of said first means except when said first switch means is conducting.

Claim 32

Dependent Claim 119 words

A logic gate comprising: a first switch means having an input terminal connected to a first logic level source, an output terminal which is the output of said gate and a control terminal which is an input of said gate and controls the conduction between said input and output terminals of said first switch means; a first precharge means connected to said output terminal of said first switch means for precharging said output terminal of said first switch means to a second logic level; and a maintaining means connected to said output of said gate for maintaining said gate output at said second logic level after deactivation of said first means except when said first switch means is conducting.

Claim 33

Dependent Claim 80 words

A logic gate according to claim 26 including a second switch means having an input terminal connected to said first logic level source, an output connected to said gate output and a control terminal which is another input of said gate and controls the conduction between said input and output terminals of said second switch means, and said maintaining means maintains said gate output at said second logic level except when either said first or second switch means are conducting.

Claim 34

Dependent Claim 99 words

A logic gate according to claim 26 including a second switch means in series between said first switch means and said first logic level source having an input terminal connected to said first logic level source, an output terminal connected to said input terminal of said first switch means, and a control terminal which is another input of said gate and controls the conduction between said input and output terminals of said second switch means, and said maintaining means maintains said gate output at said second logic level except when both said first and second switch means are conducting.

Claim 35

Dependent Claim 37 words

A logic gate according to claim 28 including a second precharge means connected to said output terminal of said second switch means for precharging said output terminal of said second switch means to said second logic level.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1988-12-16	1989-06-17	1989-12-17	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1992-12-16	1993-06-17	1993-12-17	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1996-12-16	1997-06-17	1997-12-17	$7700.00	Window Closed / Lapsed

Arithmetic logic unit

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