Method of fabricating density intensive non-self-aligned stacked CMOS

Claim 1

A method of fabricating stacked field effect semiconductor devices with channel length L, channel width W and with a maximum patterning alignment error S, comprising the steps of: (a) patterning first source and drain regions in a semiconductor substrate, said first source and drain regions of width W and defining a first channel region in said substrate of length L and width W, (b) forming a first insulating layer on said substrate and covering said first channel region, (c) patterning a conducting strip of width of L+2S on said insulating layer, said conducting strip oriented perpendicular to said length L of said first channel region and aligned without regard to S to centrally cover said first channel region, (d) forming a second insulating layer on said conducting strip and connecting to said first insulating layer, (e) patterning a semiconducting strip of width W on said insulating layers, said semiconducting strip oriented parallel to said length L of said first channel region and aligned without regard to S to cover said first channel region, (f) patterning second source and drain regions in said semiconducting strip, said second source and drain regions defining a second channel region of length L oriented perpendicular to said conducting strip and aligned without regard to S to be centrally over said conducting strip, and (g) said first source and drain regions, said first channel region, and said conducting strip forming a first field effect semiconductor device, and said second source and drain regions, said second channel region, and said conducting strip forming a secnd field effect semiconducting device stacked on said first device.

Claim 2

A method of fabricating stacked field effect semiconductor devices with channel length L, channel width W and with a maximum patterning alignment error S, comprising the steps of: (a) patterning first source and drain regions in a semiconductor substrate, said first source and drain regions of width W and defining a first channel region in said substrate of length L and width W, (b) forming a first insulating layer on said substrate and covering said first channel region, (c) patterning a conducting strip of width of L+2S on said insulating layer, said conducting strip oriented perpendicular to said length L of said first channel region and aligned without regard to S to centrally cover said first channel region, (d) forming a second insulating layer on said conducting strip and connecting to said first insulating layer, (e) patterning a semiconducting strip of width W on said insulating layers, said semiconducting strip oriented parallel to said length L of said first channel region and aligned without regard to S to cover said first channel region, (f) patterning second source and drain regions in said semiconducting strip, said second source and drain regions defining a second channel region of length L oriented perpendicular to said conducting strip and aligned without regard to S to be centrally over said conducting strip, and (g) said first source and drain regions, said first channel region, and said conducting strip forming a first field effect semiconductor device, and said second source and drain regions, said second channel region, and said conducting strip forming a secnd field effect semiconducting device stacked on said first device.

Claim 3

A method of fabricating stacked field effect semiconductor devices with channel length L, channel width W, in the underlying device, channel length K, channel width V in the overlying device, and with a maximum patterning alignment error S, comprising the steps of: (a) patterning first source and drain regions in a semiconductor substrate, said first source and drain regions of width W and defining a first channel region in said substrate of length L and width W, (b) forming a first insulating layer on said substrate and covering said first channel region, (c) patterning a conducting strip of width at least the larger of L+2S and K+2S on said insulating layer, said conducting strip oriented perpendicular to said length L of said first channel region and covering said first channel region, (d) forming a second insulating layer on said conducting strip and connecting to said first insulating layer, (e) patterning a semiconducting strip of width V on said insulating layers, said semiconducting strip oriented parallel to said length L of said first channel region and at least partially covering said first channel region, (f) patterning second source and drain regions in said semiconducting strip, said second source and drain regions defining a second channel region of length K and width V and oriented perpendicular to said conducting strip and over said conducting strip, and (g) said first source and drain regions, said first channel region, and said conducting strip forming a first field effect semiconductor device, and said second source and drain regions, said second chanel region, and said conducting strip forming a second field effect semiconducting device stacked on said first device.

Claim 4

A method of fabricating stacked field effect semiconductor devices with channel length L, channel width W, in the underlying device, channel length K, channel width V in the overlying device, and with a maximum patterning alignment error S, comprising the steps of: (a) patterning first source and drain regions in a semiconductor substrate, said first source and drain regions of width W and defining a first channel region in said substrate of length L and width W, (b) forming a first insulating layer on said substrate and covering said first channel region, (c) patterning a conducting strip of width at least the larger of L+2S and K+2S on said insulating layer, said conducting strip oriented perpendicular to said length L of said first channel region and covering said first channel region, (d) forming a second insulating layer on said conducting strip and connecting to said first insulating layer, (e) patterning a semiconducting strip of width V on said insulating layers, said semiconducting strip oriented parallel to said length L of said first channel region and at least partially covering said first channel region, (f) patterning second source and drain regions in said semiconducting strip, said second source and drain regions defining a second channel region of length K and width V and oriented perpendicular to said conducting strip and over said conducting strip, and (g) said first source and drain regions, said first channel region, and said conducting strip forming a first field effect semiconductor device, and said second source and drain regions, said second chanel region, and said conducting strip forming a second field effect semiconducting device stacked on said first device.