US4555644A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output interface for a three-state logic circuit in an integrated circuit using MOS transistors
Assignee: STMicroelectronics SRL
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Filing: 1983-12-12
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Granted: 1985-11-26
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Expires: 2003-12-12
Abstract
Abstract An output interface which includes a capacitor which is charged to a relatively high voltage by a voltage source which may have a high internal impedance, and a switching circuit which is controlled by an output of the associated logic circuit and which connects the capacitor with a gate electrode of a transistor of the final stage of the interface in order to bias it at a higher voltage than that of the power supply only during a prespecified logic state of the logic circuit and which keeps the capacitor essentially isolated (i.e.--floating) during any other logic state.
Inventors
- 👤 Daniele Devecchi
- 👤 Guido Torelli
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:42
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
374 words
An output interface circuit for a three-state logic circuit in an integrated circuit using MOS transistors having a single type of charge carriers, comprising: a supply voltage source having first and second power supply terminals; an output stage having first and second enhancement type transistors which are connected in series between said first and second terminals of said supply voltage source, said output stage having an output terminal constituting a junction point between a drain electrode of said first transistor and a source electrode of said second transistor, gate electrodes of said first and second transistors being respectively connected to a first and a second output of said three-state logic circuit so as to provide an output at said output terminal of said output stage which corresponds to the three states of said three-state logic circuit which in turn correspond to combinations of binary logic states of said first and second outputs of said three-state logic circuit; wherein a connecting and biasing network is connected between said gate electrode of said second transistor and said second output of said three-state logic circuit, said connecting and biasing network having an auxiliary feed terminal which is connected to a first terminal of an auxiliary voltage supply for supplying a predetermined voltage which is higher than that of said supply voltage source, said auxiliary voltage supply having a second terminal which is connected to said first terminal of said supply voltage source, said connecting and biasing network comprising: a capacitive element having a first electrode which is connected to said auxiliary feed terminal and having a second electrode which is connected to said first terminal of said supply voltage source; a switching means connected to said gate electrode of said second transistor and to said first electrode of said capacitive element and to said second output of said three-state logic circuit, said switching means connecting said first electrode of said capacitive element to said gate electrode of said second transistor via a low-resistance path when said second output of said logic circuit is in a predetermined binary state and substantially isolating said capacitive element when said second output of said logic circuit is in a binary logic state which is opposite to said predetermined binary logic state.
Claim 2
Dependent Claim
374 words
An output interface circuit for a three-state logic circuit in an integrated circuit using MOS transistors having a single type of charge carriers, comprising: a supply voltage source having first and second power supply terminals; an output stage having first and second enhancement type transistors which are connected in series between said first and second terminals of said supply voltage source, said output stage having an output terminal constituting a junction point between a drain electrode of said first transistor and a source electrode of said second transistor, gate electrodes of said first and second transistors being respectively connected to a first and a second output of said three-state logic circuit so as to provide an output at said output terminal of said output stage which corresponds to the three states of said three-state logic circuit which in turn correspond to combinations of binary logic states of said first and second outputs of said three-state logic circuit; wherein a connecting and biasing network is connected between said gate electrode of said second transistor and said second output of said three-state logic circuit, said connecting and biasing network having an auxiliary feed terminal which is connected to a first terminal of an auxiliary voltage supply for supplying a predetermined voltage which is higher than that of said supply voltage source, said auxiliary voltage supply having a second terminal which is connected to said first terminal of said supply voltage source, said connecting and biasing network comprising: a capacitive element having a first electrode which is connected to said auxiliary feed terminal and having a second electrode which is connected to said first terminal of said supply voltage source; a switching means connected to said gate electrode of said second transistor and to said first electrode of said capacitive element and to said second output of said three-state logic circuit, said switching means connecting said first electrode of said capacitive element to said gate electrode of said second transistor via a low-resistance path when said second output of said logic circuit is in a predetermined binary state and substantially isolating said capacitive element when said second output of said logic circuit is in a binary logic state which is opposite to said predetermined binary logic state.
Claim 3
Dependent Claim
150 words
An output interface circuit as recited in claim 1, wherein said connecting and biasing network further comprises: an enhancement type pilot transistor having its source electrode connected to said first terminal of said supply voltage source and having its drain electrode connected to said gate electrode of said second transistor; a first depletion type transistor having its drain electrode connected to said second power supply terminal of said supply voltage source and having its source electrode connected via a resistive element to said drain electrode of said pilot transistor, gate electrodes of said pilot transistor and said first depletion transistor being connected together to said second output of said three-state logic circuit; a second depletion transistor having its source, drain, and gate electrode respectively connected to said source electrode of said first depletion transistor and said first electrode of said capacitive element and said gate electrode of said second transistor.
Claim 4
Dependent Claim
25 words
An output interface as recited in claim 2, wherein said resistive element comprises a depletion type transistor having its source and gate electrodes connected together.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-25 | 1989-05-27 | 1989-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-25 | 1993-05-27 | 1993-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-25 | 1997-05-27 | 1997-11-26 | $7700.00 | Window Closed / Lapsed |