Patent US4554728A successfully refreshed from Google Patents.
US4554728A
Expired / Lapsed
US
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Simplified planarization process for polysilicon filled trenches
Assignee: International Business Machines Corp
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Filing: 1984-06-27
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Granted: 1985-11-26
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Expires: 2004-06-27
Abstract
Abstract The method of planarizing polysilicon-filled trenches involves first filling the trenches with an undoped polysilicon until the upper surface is substantially planar. The polycrystalline silicon is then heavily doped by means of diffusion of a dopant from the upper surface. The time and temperature of the diffusion are carefully controlled providing for the dopant to penetrate the polysilicon to a depth level with the tops of the trenches. A selective etchant is then utilized which removes the heavily doped polysilicon and leaves the undoped polysilicon untouched in the trenches.
Inventors
- 👤 Joseph F. Shepard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:39
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/40; H10P; H10P32/00; H10P32/30; H10P32/302; H10W10/01; H10W10/041; Y; Y10; Y10S; Y10S148/00; Y10S148/035; Y10S148/05; Y10S438/00; Y10S438/914; Y10S438/924
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
180 words
A method of forming dielectric isolation in a semiconductor substrate comprising the steps of: forming a pattern of trenches into one surface of said semiconductor substrate; forming conformally an insulating layer on said substrate and in said trenches; forming a single semiconductor layer over the insulating layer thereby filling the trenches and covering the upper surface of the insulated substrate until the top of said semiconductor layer is substantially planar; introducing in a vertically downward direction an impurity into the semiconductor layer from the top surface of said semiconductor layer to the depth of the upper surface of the insulated substrate whereby the impurity concentration of the semiconductor layer found in the trenches is substantially lower than the impurity concentration of the semiconductor layer found above the level of and on the upper surface of the insulated substrate; and, selectively removing the semiconductor layer found above the level of and on the upper surface of the insulated substrate by utilizing the difference in impurity concentrations, whereby is obtained semiconductor-filled trenches having upper surfaces in substantial planarity with the substrate surface.
Claim 2
Independent Claim
180 words
A method of forming dielectric isolation in a semiconductor substrate comprising the steps of: forming a pattern of trenches into one surface of said semiconductor substrate; forming conformally an insulating layer on said substrate and in said trenches; forming a single semiconductor layer over the insulating layer thereby filling the trenches and covering the upper surface of the insulated substrate until the top of said semiconductor layer is substantially planar; introducing in a vertically downward direction an impurity into the semiconductor layer from the top surface of said semiconductor layer to the depth of the upper surface of the insulated substrate whereby the impurity concentration of the semiconductor layer found in the trenches is substantially lower than the impurity concentration of the semiconductor layer found above the level of and on the upper surface of the insulated substrate; and, selectively removing the semiconductor layer found above the level of and on the upper surface of the insulated substrate by utilizing the difference in impurity concentrations, whereby is obtained semiconductor-filled trenches having upper surfaces in substantial planarity with the substrate surface.
Claim 3
Dependent Claim
23 words
The method of forming dielectric isolation in a semiconductor substrate as found in claim 1, wherein the semiconductor substrate is comprised of silicon.
Claim 4
Dependent Claim
28 words
The method of forming dielectric isolation in a semiconductor substrate as found in claim 2 wherein the insulating layer is SiO 2 formed by oxidation of the silicon.
Claim 5
Dependent Claim
26 words
The method of forming dielectric isolation in a semiconductor substrate as found in claim 1 wherein said semiconductor substrate layer is comprised of undoped polycrystalline silicon.
Claim 6
Dependent Claim
41 words
The method of forming dielectric isolation in a semiconductor substrate as found in claim 4 wherein the impurity introduced into the polycrystalline silicon is an n-type impurity diffused in from the top surface in an ambient atmosphere of POCl 3 .
Claim 7
Dependent Claim
35 words
The method of claim 5 whereby the selective removal is accomplished by a wet etch of 20 HNO 3 :1HF, removing the heavily doped excess layer and leaving the nominally doped polysilicon in the trenches.
Claim 8
Dependent Claim
14 words
The method of claim 1 whereby the impurity introduction is by a diffusion process.
Claim 9
Independent Claim
168 words
A method of forming dielectric isolation in a semiconductor substrate comprising: providing a silicon substrate having a planar surface; forming at least one trench on the planar surface of said substrate; forming conformally a silicon dioxide layer on said substrate planar surface and the surfaces of said trench; depositing an undoped polysilicon layer over the oxide layer, filling said trench and covering the upper surface of the oxide-covered substrate until top of the deposited polysilicon is substantially planar; diffusing in a vertically downward direction an impurity into said polysilicon from the top surface thereof to the depth of the upper surface of the oxide-covered substrated to render the polysilicon found above the level of and on the upper surface of the oxide-covered substrate highly doped while maintaining the polysilicon found in said trench undoped; and selectively etching said heavily doped polysilicon while leaving in tact said undoped polysilicon; whereby is obtained at least one polysilicon-filled trench having an upper surface in substantial planarity with the substrate planar surface.
Claim 10
Independent Claim
168 words
A method of forming dielectric isolation in a semiconductor substrate comprising: providing a silicon substrate having a planar surface; forming at least one trench on the planar surface of said substrate; forming conformally a silicon dioxide layer on said substrate planar surface and the surfaces of said trench; depositing an undoped polysilicon layer over the oxide layer, filling said trench and covering the upper surface of the oxide-covered substrate until top of the deposited polysilicon is substantially planar; diffusing in a vertically downward direction an impurity into said polysilicon from the top surface thereof to the depth of the upper surface of the oxide-covered substrated to render the polysilicon found above the level of and on the upper surface of the oxide-covered substrate highly doped while maintaining the polysilicon found in said trench undoped; and selectively etching said heavily doped polysilicon while leaving in tact said undoped polysilicon; whereby is obtained at least one polysilicon-filled trench having an upper surface in substantial planarity with the substrate planar surface.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-11-25 | 1989-05-27 | 1989-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-11-25 | 1993-05-27 | 1993-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-11-25 | 1997-05-27 | 1997-11-26 | $7700.00 | Window Closed / Lapsed |