Dynamic MOS random access memory

Claim 2

A dynamic random access memory which includes memory cells that need to be periodically refreshed, internal circuits that are brought into precharged statuses and thereafter into operating statuses, and means for accessing said memory cells in response to an address strobe signal that is supplied said dynamic random access memory, said dynamic random access memory comprising: a pulse generator which generates refresh pulses upon detecting inhibition of the supply of the address strobe signal to said dynamic random access memory; and an address counter which forms refresh address data by counting the refresh pulses, wherein a refresh timing of the memory cells specified by said address counter is determined by the refresh pulses in accordance with the inhibition of said address strobe signal to said dynamic random access memory.

Claim 3

A dynamic random access memory according to claim 1, further comprising: a timing pulse generator which generates precharging pulses for bringing said internal circuits into the precharged statuses when the supply of the address strobe signal to said dynamic random access memory is inhibited, and which generates control pulses for bringing said internal circuits into the operating statuses when the address strobe signal is supplied to said dynamic random access memory.

Claim 4

A dynamic random access memory according to claim 2, wherein said pulse generator is comprised of a first circuit which detects the inhibition of the supply of the address strobe signal to said dynamic random access memory and which produces a detection output signal upon detection of the inhibition of the supply of the address strobe signal, and a second circuit which is started by a detection output signal of said first circuit and which generates a refresh pulse in response to the receipt of said detection output signal by said second circuit.

Claim 5

A dynamic random access memory according to claim 3, wherein said second circuit is comprised of a controlled oscillator circuit, and further comprising means for controlling start and stop times of said controlled oscillator circuit in accordance with the detection output signal of said first circuit so that the refresh pulses are periodically generated in a time interval during which the address strobe signal is not supplied to said dynamic random access memory.

Claim 6

A dynamic random access memory according to claim 4, wherein said first circuit includes a delay circuit which is comprised of an integrator circuit, wherein a delay time for said delay circuit is set so that the refresh pulses are generated after the end of a precharging operation of said internal circuits which precharging operation is started when the supply of the address strobe signal to said dynamic random access memory has been inhibited.

Claim 7

A dynamic random access memory according to claim 5, including means for setting a time interval between one refresh pulse to be delivered from said controlled oscillator circuit and another refresh pulse to be subsequently delivered to be longer than a time interval which is required for precharging said internal circuits.

Claim 8

A dynamic random access memory according to claim 2, wherein said pulse generator includes a delay circuit which is comprised of an integrator circuit, wherein a delay time for said delay circuit is set so that the refresh pulses are generated after the end of a precharge operation of said internal circuits which precharge operation is started when the supply of the address strobe signal to said dynamic random access memory is inhibited.

Claim 9

A dynamic random access memory according to claim 2, wherein said pulse generator is comprised of a controlled oscillator circuit whose operation is controlled by the address strobe signal.

Claim 10

A dynamic random access memory according to claim 2, wherein said address strobe signal is applied to said dynamic random access memory through an external terminal of said dynamic random access memory.

Claim 11

A dynamic random access memory comprising: a memory cell array including a plurality of memory cells; internal circuits coupled to said memory cell array for performing reading and writing operations with regard to said memory cell array in accordance with externally applied control signals; memory access means coupled to said memory cell array including means for selecting individual memory cells in said memory array for said reading and writing operations in response to externally applied address signals upon the application of an address strobe signal to said dynamic random access memory; precharging means coupled to said internal circuits and coupled to receive said address strobe signal, said precharging means including means for supplying precharging signals to said internal circuits when an address strobe signal is not being applied to said dynamic random access memory; and refresh means coupled to receive said address strobe signal, said refresh means including means for inhibiting said precharging means for a predetermined period of time when said address strobe signal is not being applied to said dynamic random access memory and means for providing refresh signals to said memory cells during said predetermined period of time.

Claim 12

A dynamic random access memory comprising: a memory cell array including a plurality of memory cells; internal circuits coupled to said memory cell array for performing reading and writing operations with regard to said memory cell array in accordance with externally applied control signals; memory access means coupled to said memory cell array including means for selecting individual memory cells in said memory array for said reading and writing operations in response to externally applied address signals upon the application of an address strobe signal to said dynamic random access memory; precharging means coupled to said internal circuits and coupled to receive said address strobe signal, said precharging means including means for supplying precharging signals to said internal circuits when an address strobe signal is not being applied to said dynamic random access memory; and refresh means coupled to receive said address strobe signal, said refresh means including means for inhibiting said precharging means for a predetermined period of time when said address strobe signal is not being applied to said dynamic random access memory and means for providing refresh signals to said memory cells during said predetermined period of time.

Claim 13

A dynamic random access memory according to claim 10, wherein said refresh means comprises: means for determining a first point of time when an address strobe signal has stopped being applied to said dynamic random access memory, at which said first point of time said precharging means is activated to provide said precharging signals to said internal circuits; means for producing an inhibit signal at a predetermined second point of time subsequent to said first point of time for inhibiting said precharging means from providing said precharging signals to said internal circuits; means for producing said refresh signals for a predetermined period of time T R following said second point of time, during which said predetermined time T R said precharging means remains inhibited; and means for reactivating said precharging means at a third point of time after said predetermined period of time T R to again provide said precharging signals to said internal circuits while said address strobe signal is not being applied to said dynamic random access memory.

Claim 14

A dynamic random access memory according to claim 11, wherein said means for producing an inhibit signal comprises a pulse generator including an integrator for providing a predetermined delay time following the first point of time during which said predetermined delay time said precharging means is activated, and an oscillator for producing a timing pulse having a time period corresponding to T R to inhibit said precharging means while simultaneously generating said refresh signals.

Claim 15

A dynamic random access memory according to claim 11, wherein said oscillator produces a plurality of said timing pulses having said time period T R and spaced apart from one another by a predetermined period of time to intermittently inhibit said precharging means and simultaneously provide said refresh signals to said memory cells following said third point of time until such time as said address strobe signal is again applied to said dynamic random acces memory.

Claim 16

A dynamic random access memory formed as an integrated circuit on a single semiconductor substrate which includes memory cells that need to be periodically refreshed, internal circuits that are brought into precharged statuses and thereafter into operating statuses, and means for accessing said memory cells in response to an address strobe signal that is supplied to said dynamic random access memory, said dynamic random access memory having a refreshing means for providing refresh pulses to said memory cells without the need for an external terminal being provided for supplying said refresh pulses, said refreshing means comprising: a pulse generator which generates said refresh pulses internally within said integrated circuit upon detecting inhibition of the supply of the address strobe signal to said dynamic random access memory; and an address counter which forms refresh address data by counting the refresh pulses, wherein a refresh timing of the memory cells specified by said address counter is determined by the refresh pulses in accordance with the inhibition of said address strobe signal to said dynamic random access memory.

Claim 17

A dynamic random access memory formed as an integrated circuit on a single semiconductor substrate which includes memory cells that need to be periodically refreshed, internal circuits that are brought into precharged statuses and thereafter into operating statuses, and means for accessing said memory cells in response to an address strobe signal that is supplied to said dynamic random access memory, said dynamic random access memory having a refreshing means for providing refresh pulses to said memory cells without the need for an external terminal being provided for supplying said refresh pulses, said refreshing means comprising: a pulse generator which generates said refresh pulses internally within said integrated circuit upon detecting inhibition of the supply of the address strobe signal to said dynamic random access memory; and an address counter which forms refresh address data by counting the refresh pulses, wherein a refresh timing of the memory cells specified by said address counter is determined by the refresh pulses in accordance with the inhibition of said address strobe signal to said dynamic random access memory.

Claim 18

A dynamic random access memory according to claim 14, further comprising: a timing pulse generator which generates precharging pulses for bringing said internal circuits into the precharged statuses when the supply of the address strobe signal to said dynamic random access memory is inhibited, and which generates control pulses for bringing said internal circuits into the operating statuses when the address strobe signal is supplied to said dynamic random access memory.

Claim 19

A dynamic random access memory according to claim 15, wherein said address strobe signal is applied to said dynamic random access memory through an external terminal of said dynamic random access memory.

Claim 20

A dynamic random access memory formed as an integrated circuit on a single semiconductor substrate comprising: a memory cell array including a plurality of memory cells; internal circuits coupled to said memory cell array for performing reading and writing operations with regard to said memory cell array in accordance with externally applied control signals; memory access means coupled to said memory cell array including means for selecting individual memory cells in said memory array for said reading and writing operations in response to externally applied address signals upon the application of an address strobe signal to said dynamic random access memory; precharging means coupled to said internal circuits and coupled to receive said address strobe signal, and precharging means including means for supplying precharging signals to said internal circuits when an address strobe signal is not being applied to said dynamic random access memory; and refresh means coupled to receive said address strobe signal, said refresh means including means for inhibiting said precharging means for a predetermined period of time when said address strobe signal is not being applied to said dynamic random access memory and means for generating refresh signals to be provided to said memory cells during said predetermined period of time, said refresh signals being generated internally within said integrated circuit without the need for an external terminal being provided to supply refresh signals.

Claim 21

A dynamic random access memory formed as an integrated circuit on a single semiconductor substrate comprising: a memory cell array including a plurality of memory cells; internal circuits coupled to said memory cell array for performing reading and writing operations with regard to said memory cell array in accordance with externally applied control signals; memory access means coupled to said memory cell array including means for selecting individual memory cells in said memory array for said reading and writing operations in response to externally applied address signals upon the application of an address strobe signal to said dynamic random access memory; precharging means coupled to said internal circuits and coupled to receive said address strobe signal, and precharging means including means for supplying precharging signals to said internal circuits when an address strobe signal is not being applied to said dynamic random access memory; and refresh means coupled to receive said address strobe signal, said refresh means including means for inhibiting said precharging means for a predetermined period of time when said address strobe signal is not being applied to said dynamic random access memory and means for generating refresh signals to be provided to said memory cells during said predetermined period of time, said refresh signals being generated internally within said integrated circuit without the need for an external terminal being provided to supply refresh signals.

Claim 22

A dynamic random access memory according to claim 17, wherein said refresh means comprises: means for determining a first point of time when an address strobe signal has stopped being applied to said dynamic random access memory, at which said first point of time said precharging means is activated to provide said precharging signals to said internal circuits; means for producing an inhibit signal at a predetermined second point of time subsequent to said first point of time for inhibiting said precharging means from providing said precharging signals to said internal circuits; means for producing said refresh signals for a predetermined period of time T R following said second point of time, during which said predetermined time T R said precharging means remains inhibited; and means for reactivating said precharging means at a third point of time after said predetermined period of time T R to again provide said precharging signals to said internal circuits while said address strobe signal is not being applied to said dynamic random access memory.

Claim 23

A dynamic random access memory according to claim 18, wherein said means for producing an inhibit signal comprises a pulse generator including an integrator for providing a predetermined delay time following the first point of time during which said predetermined delay time said precharging means is activated, and an oscillator for producing a timing pulse having a time period corresponding to T R to inhibit said precharging means while simultaneously generating said refresh signals.

Claim 24

A dynamic random access memory according to claim 18, wherein said oscillator produces a plurality of said timing pulses having said time period T R and spaced apart from one another by a predetermined period of time to intermittently inhibit said precharging means and simultaneously provide said refresh signals to said memory cells following said third point of time until such time as said address strobe signal is again applied to said dynamic random access memory.