EP0019142A2
Expired / Lapsed
EP
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Memory device with internal refresh
Assignee: NEC Corp
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Filing: 1980-04-29
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Granted: —
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Expires: 2000-04-29
Abstract
Abstract A two-clock multi-address input dynamic random access memory provided with internal refresh function for refreshing memory cells without receiving a refresh address information from the outside is disclosed. The memory characteristically comprises a terminal for receiving a refresh control signal, refresh address means for designating a row address to be refreshed, means for producing confirmation signal when a reset precharge of a circuit relating to a refresh operation is completed, means for storing the refresh control signal when a row address strobe signal is in active level, and means responsive to the confirmation signal and the stored refresh signal for effecting the refresh operation.
Inventors
- 👤 Akira Nagami
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 19:01
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
197 words
A memory device comprising a first terminal for receiving a row strobe signal, a second terminal for receiving a column strobe signal, a set of address terminals, a third terminal for receiving a refresh control signal, first means responsive to said row strobe signal for storing address signals applied to said address terminals as a row address information, second means responsive to said column strobe signal for storing address signals applied to said address terminals as a column address information, a memory cell matrix including memory cells arranged in rows and columns, refresh means responsive to said row strobe signal for refreshing the memory cells on the row designated by said row address information, said refresh means taking a reset precharge state in response to absence of said row strobe signal, refresh address means for designating an address of said row to be refreshed, third means for producing confirmation signal when said reset precharge state ends, fourth means for storing said refresh control signal when said row strobe signal is present, and a control means responsive to said confirmation signal and the latched refresh control signal for introducing a refresh operation based on said refresh address means.
Claim 2
Dependent Claim
197 words
A memory device comprising a first terminal for receiving a row strobe signal, a second terminal for receiving a column strobe signal, a set of address terminals, a third terminal for receiving a refresh control signal, first means responsive to said row strobe signal for storing address signals applied to said address terminals as a row address information, second means responsive to said column strobe signal for storing address signals applied to said address terminals as a column address information, a memory cell matrix including memory cells arranged in rows and columns, refresh means responsive to said row strobe signal for refreshing the memory cells on the row designated by said row address information, said refresh means taking a reset precharge state in response to absence of said row strobe signal, refresh address means for designating an address of said row to be refreshed, third means for producing confirmation signal when said reset precharge state ends, fourth means for storing said refresh control signal when said row strobe signal is present, and a control means responsive to said confirmation signal and the latched refresh control signal for introducing a refresh operation based on said refresh address means.
Claim 3
Dependent Claim
22 words
The memory device according to claim 1, further comprising means responsive to said refresh control signal for controlling said refresh address means.
Claim 4
Dependent Claim
41 words
The memory device according to claim 2, further comprising a data bus line and selection means responsive to said column strobe signal for coupling a memory cell on the column designated by said column address information with said date bus line.
Claim 5
Dependent Claim
38 words
The memory device according to claim 3, further comprising means for producing completion signal when refresh operation is completed, and means responsive to said completion signal for introducing said reset precharge state into at least said refresh means.
Claim 6
Dependent Claim
200 words
In a dynamic random access memory having as input signals a row strobe signal, a column strobe signal, a multiaddress input signal, and a refresh control signal, having a function that, first by enabling the row strobe signal, data stored in all the memory cells on a row line designated by an address input at this time are automatically refreshed and by enabling the column strobe signal, data between a selected memory cell on the column line designated by the address input at this time and a data input/output circuit is automatically transferred and having a refresh address mean s in which when said refresh control signal is enabled, the said refresh is internally performed, the improvement comprises first means for producing a first confirmation signal at the end of active operation and a second means producing a second confirmation signal at the end of a reset precharge operation, third means for storing said refresh control signal when said row strobe signal is in active level, fourth means responsive to said second confirmation signal and the stored refresh control signal for effecting the internal refresh operation, and fifth means responsive to said first confirmation signal for effecting reset precharge operation.
Claim 7
Dependent Claim
200 words
In a dynamic random access memory having as input signals a row strobe signal, a column strobe signal, a multiaddress input signal, and a refresh control signal, having a function that, first by enabling the row strobe signal, data stored in all the memory cells on a row line designated by an address input at this time are automatically refreshed and by enabling the column strobe signal, data between a selected memory cell on the column line designated by the address input at this time and a data input/output circuit is automatically transferred and having a refresh address mean s in which when said refresh control signal is enabled, the said refresh is internally performed, the improvement comprises first means for producing a first confirmation signal at the end of active operation and a second means producing a second confirmation signal at the end of a reset precharge operation, third means for storing said refresh control signal when said row strobe signal is in active level, fourth means responsive to said second confirmation signal and the stored refresh control signal for effecting the internal refresh operation, and fifth means responsive to said first confirmation signal for effecting reset precharge operation.
References Cited (Backward Citations)
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