Patent US4546486A successfully refreshed from Google Patents.
US4546486A
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Clock recovery arrangement
Assignee: Ericsson Inc
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Filing: 1983-08-29
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Granted: 1985-10-08
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Expires: 2003-08-29
Abstract
Abstract A clock recovery arrangement particularly suitable for recovering a clock signal from Manchester-encoded data. The system includes a locally generated clock at twice the data rate. This locally generated clock is phase locked to the incoming data transitions. Then, the locked locally generated clock is divided by two to produce a clock signal corresponding to the data rate. A clock flipper circuit operating according to a predetermined algorithm determines whether to change the polarity of the clock signal to provide a correct polarity recovered clock.
Inventors
- 👤 Michael W. Evans
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:27
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0331; H04L7/0337
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
175 words
A clock recovery arrangement for recovering a clock signal at a first frequency, which clock signal is synchronized to a received data stream having a characteristic data bit frequency equal to said first frequency, comprising: means for detecting edge transitions of said data stream and producing an edge signal indicative thereof; means for generating a local second frequency clock signal, said second frequency being twice that of said first frequency, said second frequency clock signal not being phase synchronized with said received data stream; means for phase locking said second frequency clock signal to said edge transitions to produce a phase locked second frequency clock; means for dividing said phase locked second frequency clock by two to produce a clock signal at said first frequency that is phase locked to said edge signal and therefore phase locked to said received data stream; and means for changing the polarity of said phase locked first frequency clock according to a predetermined function of said edge signals, thereby producing a received clock synchronized to said received data stream.
Claim 2
Dependent Claim
175 words
A clock recovery arrangement for recovering a clock signal at a first frequency, which clock signal is synchronized to a received data stream having a characteristic data bit frequency equal to said first frequency, comprising: means for detecting edge transitions of said data stream and producing an edge signal indicative thereof; means for generating a local second frequency clock signal, said second frequency being twice that of said first frequency, said second frequency clock signal not being phase synchronized with said received data stream; means for phase locking said second frequency clock signal to said edge transitions to produce a phase locked second frequency clock; means for dividing said phase locked second frequency clock by two to produce a clock signal at said first frequency that is phase locked to said edge signal and therefore phase locked to said received data stream; and means for changing the polarity of said phase locked first frequency clock according to a predetermined function of said edge signals, thereby producing a received clock synchronized to said received data stream.
Claim 3
Dependent Claim
19 words
A clock recovery arrangement according to claim 1 wherein said phase locking means comprises a digital phase locked loop.
Claim 4
Dependent Claim
43 words
A clock recovery arrangement according to claim 1 wherein said second frequency clock generating means comprises: an oscillator operating at a multiple of said second frequency; and a divider, coupled to said oscillator for dividing down said oscillator frequency to said second frequency.
Claim 5
Dependent Claim
84 words
A clock recovery arrangement according to claim 3 wherein said phase locking means comprises: a phase detector for detecting a phase difference between said edge signal and said second frequency clock signal and producing in response thereto control signals; and an up/down counter, responsive to said control signals for counting pulses of said oscillator and in response thereto generating signals coupled to said divider for controlling addition and deletion of a pulse count thereof so as to synchronize its output with said edge signal.
Claim 6
Dependent Claim
41 words
A clock recovery arrangement according to claim 2 wherein said phase detector comprises means for generating said control signals including one such signal having a pulse width proportional to the phase difference between said edge signal and said second frequency clock.
Claim 7
Dependent Claim
17 words
A clock recovery arrangement according to claim 1 wherein said data stream is in a return-to-zero format.
Claim 8
Dependent Claim
16 words
A clock recovery arrangement according to claim 6 wherein said data stream comprises Manchester coded data.
Claim 9
Dependent Claim
160 words
A data and clock recovery system comprising: means for receiving a data stream having a first characteristic data bit frequency; means for detecting edge transitions of said data stream and producing an edge signal indicative thereof; means for generating a local second frequency clock signal, said second frequency being twice that of said first frequency, said second frequency clock signal not being phase synchronized with said received data stream; means for phase locking said second frequency clock signal to said edge transitions to produce a phase locked second frequency clock; means for dividing said phase locked second frequency clock by two to produce a clock signal at said first frequency that is phase locked to said edge signal and therefore phase locked to said received data stream; and means for changing the polarity of said phase locked first frequency clock according to a predetermined function of said edge signals, thereby producing a received clock synchronized to said received data stream.
Claim 10
Dependent Claim
160 words
A data and clock recovery system comprising: means for receiving a data stream having a first characteristic data bit frequency; means for detecting edge transitions of said data stream and producing an edge signal indicative thereof; means for generating a local second frequency clock signal, said second frequency being twice that of said first frequency, said second frequency clock signal not being phase synchronized with said received data stream; means for phase locking said second frequency clock signal to said edge transitions to produce a phase locked second frequency clock; means for dividing said phase locked second frequency clock by two to produce a clock signal at said first frequency that is phase locked to said edge signal and therefore phase locked to said received data stream; and means for changing the polarity of said phase locked first frequency clock according to a predetermined function of said edge signals, thereby producing a received clock synchronized to said received data stream.
Claim 11
Dependent Claim
19 words
A clock recovery arrangement according to claim 8 wherein said phase locking means comprises a digital phase locked loop.
Claim 12
Dependent Claim
43 words
A clock recovery arrangement according to claim 8 wherein said second frequency clock generating means comprises: an oscillator operating at a multiple of said second frequency; and a divider, coupled to said oscillator for dividing down said oscillator frequency to said second frequency.
Claim 13
Dependent Claim
84 words
A clock recovery arrangement according to claim 10 wherein said phase locking means comprises: a phase detector for detecting a phase difference between said edge signal and said second frequency clock signal and producing in response thereto control signals; and an up/down counter, responsive to said control signals for counting pulses of said oscillator and in response thereto generating signals coupled to said divider for controlling addition and deletion of a pulse count thereof so as to synchronize its output with said edge signal.
Claim 14
Dependent Claim
41 words
A clock recovery arrangement according to claim 9 wherein said phase detector comprises means for generating said control signals including one such signal having a pulse width proportional to the phase difference between said edge signal and said second frequency clock.
Claim 15
Dependent Claim
17 words
A clock recovery arrangement according to claim 8 wherein said data stream is in a return-to-zero format.
Claim 16
Dependent Claim
16 words
A clock recovery arrangement according to claim 13 wherein said data stream comprises Manchester coded data.
Claim 17
Dependent Claim
156 words
An arrangement for recovering a clock from Manchester coded data having a first characteristic frequency, comprising: means for detecting edge transitions of said data stream and producing an edge signal indicative thereof; means for generating a local second frequency clock signal, said second frequency being twice that of said first frequency, said second frequency clock signal not being phase synchronized with said recovered data stream; means for phase locking said second frequency clock signal to said edge transitions to produce a phase locked second frequency clock; means for dividing said phase locked second frequency clock by two to produce a clock signal at said first frequency that is phase locked to said edge signal and therefore phase locked to said received data stream; and means for changing the polarity of said phase locked first frequency clock according to a predetermined function of said edge signals, thereby producing a recovered clock synchronized to said received data stream.
Claim 18
Dependent Claim
156 words
An arrangement for recovering a clock from Manchester coded data having a first characteristic frequency, comprising: means for detecting edge transitions of said data stream and producing an edge signal indicative thereof; means for generating a local second frequency clock signal, said second frequency being twice that of said first frequency, said second frequency clock signal not being phase synchronized with said recovered data stream; means for phase locking said second frequency clock signal to said edge transitions to produce a phase locked second frequency clock; means for dividing said phase locked second frequency clock by two to produce a clock signal at said first frequency that is phase locked to said edge signal and therefore phase locked to said received data stream; and means for changing the polarity of said phase locked first frequency clock according to a predetermined function of said edge signals, thereby producing a recovered clock synchronized to said received data stream.
Claim 19
Dependent Claim
19 words
A clock recovery arrangement according to claim 15 wherein said phase locking means comprises a digital phase locked loop.
Claim 20
Dependent Claim
43 words
A clock recovery arrangement according to claim 15 wherein said second frequency clock generating means comprises: an oscillator operating at a multiple of said second frequency; and a divider, coupled to said oscillator for dividing down said oscillator frequency to said second frequency.
Claim 21
Dependent Claim
84 words
A clock recovery arrangement according to claim 17 wherein said phase locking means comprises: a phase detector for detecting a phase difference between said edge signal and said second frequency clock signal and producing in response thereto control signals; and an up/down counter, responsive to said control signals for counting pulses of said oscillator and in response thereto generating signals coupled to said divider for controlling addition and deletion of a pulse count thereof so as to synchronize its output with said edge signal.
Claim 22
Dependent Claim
41 words
A clock recovery arrangement according to claim 16 wherein said phase detector comprises means for generating said control signals including one such signal having a pulse width proportional to the phase difference between said edge signal and said second frequency clock.
Claim 23
Dependent Claim
17 words
A clock recovery arrangement according to claim 15 wherein said data stream is in a return-to-zero format.
Claim 24
Dependent Claim
16 words
A clock recovery arrangement according to claim 20 wherein said data stream comprises Manchester coded data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-10-07 | 1989-04-08 | 1989-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-10-07 | 1993-04-08 | 1993-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-10-07 | 1997-04-08 | 1997-10-08 | $7700.00 | Window Closed / Lapsed |