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US4539636A
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Apparatus for inter-processor data transfer in a multi-processor system
Assignee: Elevator GmbH
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Filing: 1984-11-30
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Granted: 1985-09-03
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Expires: 2004-11-30
Abstract
Abstract This procedure and apparatus is used for transferring data between central units or processors in a multi-processor system. The system includes one or several central units (3) with memories (4). The data to be transferred between central units (3) or processors are separated from their internal bus (6) by means of joint memories (2) and that the data transfer between the joint memories (2) is effected by a separate copying means (1).
Inventors
- 👤 Paavo Saaksjarvi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:52
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F15/00; G06F15/16; G06F15/161; G06F15/163
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
161 words
A system for transferring data between central units of processors in a multi-processor system, said system comprising central units with central memories, an internal bus for the transmission of data between individual ones of said central units, joint memories, and copying means for clocking the joint memories; and wherein the central units of processors are separated from said internal bus by said joint memories, a data transfer among all the joint memories is effected by said copying means; each of said joint memories includes its own address generation means responsive to common clock synchronization signals of the copying means transmitted to all of the joint memories for simultaneous transfer of data without transference of address signals among all the joint memories and; all of said address generation means generate the same address concurrently in response to said clock synchronization signals without a computation of separate addresses, thereby permitting continuous transfer of data independently of any normal operation of said central units.
Claim 2
Independent Claim
161 words
A system for transferring data between central units of processors in a multi-processor system, said system comprising central units with central memories, an internal bus for the transmission of data between individual ones of said central units, joint memories, and copying means for clocking the joint memories; and wherein the central units of processors are separated from said internal bus by said joint memories, a data transfer among all the joint memories is effected by said copying means; each of said joint memories includes its own address generation means responsive to common clock synchronization signals of the copying means transmitted to all of the joint memories for simultaneous transfer of data without transference of address signals among all the joint memories and; all of said address generation means generate the same address concurrently in response to said clock synchronization signals without a computation of separate addresses, thereby permitting continuous transfer of data independently of any normal operation of said central units.
Claim 3
Dependent Claim
54 words
A system according to claim 1, characterized in that timing signals of the copying means provide for the copying of data of a writing block associated with a central unit or processor to the corresponding blocks of other ones of said central units simultaneously, the writing block being a portion of a joint memory.
Claim 4
Dependent Claim
28 words
A system according to claim 1, characterized in that transfer of data between the joint memories is carried out completely without burdening the central units or the processors.
Claim 5
Dependent Claim
55 words
A system according to claim 1, wherein, in each if said joint memories, said generation means includes an address counter, and wherein the addressing of data in a copying operation of said copying means is carried out between the joint memories by means of said address counters, said counters being synchronized by the copying means.
Claim 6
Dependent Claim
27 words
A system according to claim 1 wherein for each central unit of processor, one of said joint memories is connected to a corresponding central unit or processor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-09-02 | 1989-03-04 | 1989-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-09-02 | 1993-03-04 | 1993-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-09-02 | 1997-03-04 | 1997-09-03 | $7700.00 | Window Closed / Lapsed |