US4535530A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for manufacturing a semiconductor memory device
Assignee: Mitsubishi Electric Corp
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Filing: 1984-04-05
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Granted: 1985-08-20
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Expires: 2004-04-05
Abstract
Abstract An n-channel MOS dynamic memory cell includes a semiconductor substrate having a p + internal region and a p - surface region disposed on the surface of the internal region except for an n + region serving as a bit line, a capacitor electrode disposed above the surface region, and a transfer gate disposed between the capacitor electrode and the n + region above the surface region. The surface region except for the n + region and a portion of the internal region disposed below the transfer gate are higher in resistivity than at least one of a portion of the internal region disposed below the capacitor electrode and another portion of the internal region disposed below the n + region.
Inventors
- 👤 Masahiko Denda
- 👤 Shinichi Sato
- 👤 Natsuro Tsubouchi
- 👤 Shigeji Kinoshita
- 👤 Yoshikazu Ohbayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:43
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
196 words
A process of manufacturing a semiconductor memory device comprising the steps of: selectively implanting, into a main surface of a semiconductor substrate of a first type of conductivity, a second type of conductivity forming impurity so as to form impurity implanted regions of said first type of conductivity which are higher in resistivity than said semiconductor substrate; epitaxially growing surface regions on said semiconductor substrate including said impurity implanted regions, said surface regions being similar in resistivity to said impurity implanted regions; forming a bit line region of said second type conductivity in said surface regions except for a portion of said surface regions which are disposed on said impurity implanted regions, said bit line region reaching said semiconductor substrate from the surface of said surface regions; and forming a gate electrode of a transfer gate transistor above said surface regions and also above said impurity implanted regions through an electrically insulating material and forming through said electrically insulating material an electrode of a capacitor above a portion of said surface regions which are located opposite to said bit line region with respect to said portion of said surface regions disposed on said impurity implanted regions.
Claim 2
Dependent Claim
196 words
A process of manufacturing a semiconductor memory device comprising the steps of: selectively implanting, into a main surface of a semiconductor substrate of a first type of conductivity, a second type of conductivity forming impurity so as to form impurity implanted regions of said first type of conductivity which are higher in resistivity than said semiconductor substrate; epitaxially growing surface regions on said semiconductor substrate including said impurity implanted regions, said surface regions being similar in resistivity to said impurity implanted regions; forming a bit line region of said second type conductivity in said surface regions except for a portion of said surface regions which are disposed on said impurity implanted regions, said bit line region reaching said semiconductor substrate from the surface of said surface regions; and forming a gate electrode of a transfer gate transistor above said surface regions and also above said impurity implanted regions through an electrically insulating material and forming through said electrically insulating material an electrode of a capacitor above a portion of said surface regions which are located opposite to said bit line region with respect to said portion of said surface regions disposed on said impurity implanted regions.
Claim 3
Dependent Claim
46 words
A process of manufacturing a semiconductor memory device as claimed in claim 1, wherein said semiconductor substrate is a P type silicon substrate doped with boron and said impurity implanted regions are formed by selectively implanting phosphorus as an N type impurity into said semiconductor substrate.
Claim 4
Dependent Claim
32 words
A process of manufacturing a semiconductor memory device as claimed in claim 1, wherein said semiconductor substrate is a P type silicon substrate having a resistivity of from 1 to 0.01 Ωcm.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-08-19 | 1989-02-18 | 1989-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-08-19 | 1993-02-18 | 1993-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-08-19 | 1997-02-18 | 1997-08-20 | $7700.00 | Window Closed / Lapsed |