US4328610A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of reducing alpha-particle induced errors in an integrated circuit
Assignee: Unisys Corp
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Filing: 1980-04-25
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Granted: 1982-05-11
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Expires: 2000-04-25
Abstract
Abstract Alpha-particle induced errors in integrated circuits, especially those used for memory storage, are reduced by subjecting the partially completed, or fully completed, integrated circuits to neutron irradiation. This irradiation creates "traps" in the single crystalline semiconductor substrates of the integrated circuits for any unwanted charged particles that are produced by alpha particle radiation. Consequently, such unwanted charged particles do not disrupt the integrity of any data stored in the circuit. In one embodiment, the neutron irradiation is applied during wafer fabrication and, in a second embodiment, the irradiation is applied after wafer fabrication but before packaging of the circuit, and in the third embodiment the irradiation is applied after a completion of the packaging step of the integrated circuits.
Inventors
- 👤 Charles E. Thompson
- 👤 Roger G. Newell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:31
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10P; H10P34/00; H10P34/40; H10W; H10W42/00; H10W42/20; H10W42/25; Y; Y10; Y10S; Y10S438/00; Y10S438/953; Y10S438/98
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
61 words
In the manufacture of integrated circuit packages, the steps of: providing a semiconductor substrate, forming in said substrate capacitance means for receiving electron charges functional in the operation of said integrated circuit, and irradiating said substrate with neutrons to form electron traps in said substrate to prevent unwanted charges produced in said substrate by alpha-particle radiation from entering said capacitance means.
Claim 2
Dependent Claim
61 words
In the manufacture of integrated circuit packages, the steps of: providing a semiconductor substrate, forming in said substrate capacitance means for receiving electron charges functional in the operation of said integrated circuit, and irradiating said substrate with neutrons to form electron traps in said substrate to prevent unwanted charges produced in said substrate by alpha-particle radiation from entering said capacitance means.
Claim 3
Dependent Claim
27 words
The method as claimed in claim 1 further including the step of forming conductive paths and contacts in a desired pattern to form an operational integrated circuit.
Claim 4
Dependent Claim
21 words
The method as claimed in claim 2 further including the step of packaging said integrated circuit for use in electronic devices.
Claim 5
Dependent Claim
26 words
The method as claimed in claim 1 further including, prior to performing said irradiation, the step of forming conductive paths and contacts in a desired pattern.
Claim 6
Dependent Claim
26 words
The method as claimed in claim 1 further including, prior to performing said irradiation, the step of packaging said integrated circuit for use in electronic devices.
Claim 7
Dependent Claim
68 words
In the manufacture of a semiconductor dynamic memory circuit, the steps of: providing a semiconductor substrate, forming in said substrate capacitances as a means for receiving electron charges representing information stored in said memory, and irradiating said substrate with neutrons to form electron traps in said substrate to prevent unwanted charges produced in said substrate by alpha-particle radiation from entering said capacitances when said memory circuit is operational.
Claim 8
Dependent Claim
68 words
In the manufacture of a semiconductor dynamic memory circuit, the steps of: providing a semiconductor substrate, forming in said substrate capacitances as a means for receiving electron charges representing information stored in said memory, and irradiating said substrate with neutrons to form electron traps in said substrate to prevent unwanted charges produced in said substrate by alpha-particle radiation from entering said capacitances when said memory circuit is operational.
Claim 9
Dependent Claim
30 words
The method as claimed in claim 6 further including forming conductive bit and word lines coupling said capacitances in a matrix for accessing individual capacitances as binary bit memory cells.
Claim 10
Dependent Claim
21 words
The method as claimed in claim 7 further including the step of packaging said memory circuit for use in electron devices.
Claim 11
Dependent Claim
38 words
The method as claimed in claim 6 further including, prior to performing said irradiation, the step of forming conductive word and bit lines coupling said capacitances in a matrix for accessing individual capacitances as binary bit memory cells.
Claim 12
Dependent Claim
26 words
The method as claimed in claim 6 further including, prior to performing said irradiation, the step of packaging said memory circuit for use in electronic devices.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-05-10 | 1985-11-09 | 1986-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-05-10 | 1989-11-09 | 1990-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-05-10 | 1993-11-09 | 1994-05-11 | $7700.00 | Window Closed / Lapsed |