Patent US4529894A successfully refreshed from Google Patents.
US4529894A
Expired / Lapsed
US
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Means for enhancing logic circuit performance
Assignee: International Business Machines Corp
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Filing: 1981-06-15
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Granted: 1985-07-16
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Expires: 2001-06-15
Abstract
Abstract Disclosed is a means for enhancing logic circuit performance and more particularly, for enhancing the switching speeds of a variety of logic circuits. What is involved is the insertion of a so called "snap" or enhancement transistor connected to a common node defining an output of a basic logic circuit. In one example, the emitter of this "snap" transistor is connected to an output node in the circuit, which in conventional practice would be charged during an upgoing transition by a fixed RC time constant. In accordance with the present improvement, however, the "snap" transistor, due to charge stored therein, remains conducting--although the associated logic device is turned off. This current discharges as reverse base current and the output provides what appears to be an inductive voltage spike. The effect is that a temporary source of current is available to charge the common node. As a result, the transition time involved in going from one voltage level to another at the output node is substantially reduced.
Inventors
- 👤 Yuen H. Chan
- 👤 James E. Dickerson
- 👤 Walter S. Klara
- 👤 Theodore W. Kwap
- 👤 Joseph M. Mosley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:19
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/013; H03K19/0136
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
174 words
A logic circuit, having an input terminal and an output terminal, for providing enhanced logic or switching speed comprising: at least one logic device, having at least two electrodes, one of which is connected to the logic circuit input terminal, the other being connected to the logic circuit output terminal; a speed enhancement switching transistor having emitter, base, and collector regions; further including a common and direct connection between said emitter region of said speed enhancement switching transistor and the other of said two electrodes, said common and direct connection also being made to said output terminal; a source of potential operatively coupled to the collector path of said speed enhancement switching transistor; the speed enhancement switching transistor functioning to store charge, and including means, having substantial impedance, connected between the base region of said speed enhancement switching transistor and said source of potential, for discharging current during the transition period of the output signal so as effectively to pull up the output terminal voltage, thereby accelerating the transient slope of the output signal.
Claim 2
Dependent Claim
174 words
A logic circuit, having an input terminal and an output terminal, for providing enhanced logic or switching speed comprising: at least one logic device, having at least two electrodes, one of which is connected to the logic circuit input terminal, the other being connected to the logic circuit output terminal; a speed enhancement switching transistor having emitter, base, and collector regions; further including a common and direct connection between said emitter region of said speed enhancement switching transistor and the other of said two electrodes, said common and direct connection also being made to said output terminal; a source of potential operatively coupled to the collector path of said speed enhancement switching transistor; the speed enhancement switching transistor functioning to store charge, and including means, having substantial impedance, connected between the base region of said speed enhancement switching transistor and said source of potential, for discharging current during the transition period of the output signal so as effectively to pull up the output terminal voltage, thereby accelerating the transient slope of the output signal.
Claim 3
Dependent Claim
54 words
A logic circuit as defined in claim 1, in which both the logic device and the speed enhancement switching transistor are in the ON state together and both are in the OFF state together, the speed enhancement transistor lagging behind the logic device in the transition from one of said states to the other.
Claim 4
Dependent Claim
47 words
A logic circuit as defined in claim 1, in which said at least one logic device comprises a transistor having collector, base and emitter regions; the speed enhancement switching transistor having its emitter region connected directly to the collector region of said at least one logic transistor.
Claim 5
Dependent Claim
47 words
A logic circuit as defined in claim 3, in which said speed enhancement switching transistor has a switching speed slower than said at least one logic transistor, whereby it is assured that sufficient charge storage will be affectuated such that a required speed enhancement can be realized.
Claim 6
Dependent Claim
28 words
A logic circuit as defined in claim 1, further including means providing the charge stored in the speed enhancement switching transistor is discharged as reverse base current flow.
Claim 7
Dependent Claim
19 words
A logic circuit as defined in claim 1, in which said means having substantial impedance comprises a base resistor.
Claim 8
Dependent Claim
27 words
A logic circuit as defined in claim 5, in which a resistor is connected from the collector of said speed enhancement switching transistor directly to said source.
Claim 9
Dependent Claim
27 words
A logic circuit as defined in claim 6, in which a load resistor is connected from said common and direct connection directly to said source of potential.
Claim 10
Dependent Claim
33 words
A logic circuit as defined in claim 8, in which the ratio of emitter current I E of the speed enhancement switching transistor to current through said load resistor is greater than one.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-15 | 1989-01-14 | 1989-07-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-15 | 1993-01-14 | 1993-07-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-15 | 1997-01-14 | 1997-07-16 | $7700.00 | Window Closed / Lapsed |