Patent US4527233A successfully refreshed from Google Patents.
US4527233A
Expired / Lapsed
US
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Addressable buffer circuit with address incrementer independently clocked by host computer and external storage device controller
Assignee: Western Digital Corp
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Filing: 1982-07-26
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Granted: 1985-07-02
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Expires: 2002-07-26
Abstract
Abstract A direct buffer access circuit provides a buffer memory for use with a host central processing unit and a peripheral controller for controlling an external data storage device such as a disk or tape drive. The buffer is connected so that both the host and the controller have direct access to the buffer. The host can thus transfer data to the buffer at its own data rate independently of the transfer rate of the controller. The buffer may include either a random access memory which is addressed by a counter, or a first-in/first-out memory. The buffer is controlled by signals received from either the host or the controller.
Inventors
- 👤 William H. Ambrosius, III
- 👤 Randall Chung
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 17:49
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
239 words
A direct buffer access circuit for use in a data processing system having a host computer, an external data storage device for supplying data to the host computer, and a peripheral controller connected between the host computer and data storage device for controlling the operation of the data storage device and transferring data between the host computer and the data storage device, the direct buffer access circuit comprising: addressable memory means connected to the host computer and to the controller for receiving and storing data from the host computer for subsequent transmission to the storage device via the controller and for receiving and storing data from the storage device via the controller for subsequent transmission to the host computer and for receiving control signals from both the host computer and controller to indicate whether data is to be written into or read out of the memory means; addressing means coupled to the memory means, the host computer, and the controller for providing an incrementable address signal to the memory means; wherein the host computer provides first clocking signals to increment the addressing means to control the rate of addressing of the memory means during transfer of data between the host computer and memory means and wherein the controller provides second clocking signals to increment the addressing means to control the rate of addressing of the memory means during transfer of data between the storage device and the memory means.
Claim 2
Dependent Claim
239 words
A direct buffer access circuit for use in a data processing system having a host computer, an external data storage device for supplying data to the host computer, and a peripheral controller connected between the host computer and data storage device for controlling the operation of the data storage device and transferring data between the host computer and the data storage device, the direct buffer access circuit comprising: addressable memory means connected to the host computer and to the controller for receiving and storing data from the host computer for subsequent transmission to the storage device via the controller and for receiving and storing data from the storage device via the controller for subsequent transmission to the host computer and for receiving control signals from both the host computer and controller to indicate whether data is to be written into or read out of the memory means; addressing means coupled to the memory means, the host computer, and the controller for providing an incrementable address signal to the memory means; wherein the host computer provides first clocking signals to increment the addressing means to control the rate of addressing of the memory means during transfer of data between the host computer and memory means and wherein the controller provides second clocking signals to increment the addressing means to control the rate of addressing of the memory means during transfer of data between the storage device and the memory means.
Claim 3
Dependent Claim
30 words
A direct buffer access circuit as in claim 1 wherein the addressing means comprises a sequential counter which is incrementally clocked to change the address signal to the memory means.
Claim 4
Dependent Claim
18 words
A direct buffer access circuit as in claim 2 wherein the memory means comprises a random access memory.
Claim 5
Dependent Claim
57 words
A direct buffer access circuit as in claim 2 wherein the counter provides an indicator signal after the memory has been completely addressed, said indicator signal indicating that the memory is empty if data was being read from the memory and indicating that the memory means is full if data was being written into the memory means.
Claim 6
Dependent Claim
17 words
A direct buffer access circuit as in claim 1 wherein the memory means comprises a first-in/first-out memory.
Claim 7
Dependent Claim
58 words
A direct buffer access circuit as in claim 5 wherein the first-in/first-out memory provides an indicator signal after the memory has been completely addressed, said indicator signal indicating that the memory is empty if data was being read from the memory and indicating that the memory means is full if data was being written into the memory means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-01 | 1988-12-31 | 1989-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-01 | 1992-12-31 | 1993-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-01 | 1996-12-31 | 1997-07-02 | $7700.00 | Window Closed / Lapsed |