US4240138A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for direct access to a memory associated with a microprocessor
Assignee: Texas Instruments Inc
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Filing: 1978-10-03
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Granted: 1980-12-16
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Expires: 1998-10-03
Abstract
Abstract System for direct access to a memory associated with a microprocessor data processing device comprising a direct access interface for introducing or extracting data in the memory during interruptions of the connection between the processing device and the memory, and a buffer interface operable during a portion of the access time of the processing device to the memory, to supply data addresses contained in the memory originating from the processing device and to enable circulation of corresponding data between the processing device and the memory, and during the remainder of the access time of the processing device, to the end of the access time, to store data transferred from the memory and to prevent transmission of data to the memory. A logic circuit controls inhibition of the buffer interface or of the direct access interface and, during the periods of inhibition of the buffer interface, permits the circulation of data and of addresses between the direct access interface and the memory.
Inventors
- 👤 Gerard Chauvel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:22
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1668; G06F13/1673; G06F13/20; G06F13/28; G06F13/287
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
242 words
A data processing system comprising: memory means for providing the contents of memory locations therein a predetermined response time after receiving the location addresses thereof; data processing means for providing, during a first memory access period, a primary access control signal and a first memory location address, and for receiving, during a consecutive, second memory access period, the contents provided by the memory means in response thereto, the first and second memory access periods being at least equal to the response time of the memory means; buffer interface circuit means for applying, in an enabled condition, a memory location address provided by said data processing means to said memory means and for receiving the contents provided by the memory means in response thereto, and for providing, in a disabled condition, the received contents to the data processing means; direct access interface means for applying, in an enabled condition, a received second memory location address to the memory means, and for receiving and providing, in the enabled condition, the contents provided by the memory means in response thereto; and data flow control means for receiving the primary access control signal and an asynchronous, secondary access control signal, for enabling only said direct access interface means for at least said response time in response to receiving only the secondary access control signal, and for enabling said buffer interface means for at least said response time in response to receiving the primary access control signal.
Claim 2
Dependent Claim
242 words
A data processing system comprising: memory means for providing the contents of memory locations therein a predetermined response time after receiving the location addresses thereof; data processing means for providing, during a first memory access period, a primary access control signal and a first memory location address, and for receiving, during a consecutive, second memory access period, the contents provided by the memory means in response thereto, the first and second memory access periods being at least equal to the response time of the memory means; buffer interface circuit means for applying, in an enabled condition, a memory location address provided by said data processing means to said memory means and for receiving the contents provided by the memory means in response thereto, and for providing, in a disabled condition, the received contents to the data processing means; direct access interface means for applying, in an enabled condition, a received second memory location address to the memory means, and for receiving and providing, in the enabled condition, the contents provided by the memory means in response thereto; and data flow control means for receiving the primary access control signal and an asynchronous, secondary access control signal, for enabling only said direct access interface means for at least said response time in response to receiving only the secondary access control signal, and for enabling said buffer interface means for at least said response time in response to receiving the primary access control signal.
Claim 3
Dependent Claim
96 words
A system according to claim 1, wherein said data flow control means comprises: a first channel control for receiving and registering the primary access control signal; a second channel control for receiving and registering the secondary access control signal; and a priority control for enabling said direct access interface means for at least said response time if only a secondary access control signal is registered, the registration being reset thereafter, and for enabling the buffer interface means for at least said response time if a primary access control signal is registered, the registration being reset thereafter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-12-16 | 1984-06-16 | 1984-12-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-12-16 | 1988-06-16 | 1988-12-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-12-16 | 1992-06-16 | 1992-12-16 | $7700.00 | Window Closed / Lapsed |