CMOS D-type latch employing six transistors and four diodes

Claim 2

A D-type latch having a data input node, a data output node, and a complementary data output node, said latch comprising: first, second and third inverters each having an input node, an output node, and a pair of inverter voltage supply nodes, each of said first and third inverters capable of being selectively enabled by applying voltage polarity of one sense to its voltage supply nodes and of being selectively disabled by applying voltage polarity of the opposite sense to its voltage supply nodes, the output node of either of said first and third inverters being essentially an open circuit with respect to either logic voltage level when the particular inverter is disabled; said second inverter voltage supply nodes comprising said latch voltage supply nodes for continuously enabling said second inverter; said first and third inverter voltage supply nodes comprising complementary clock input nodes such that, when said clock input nodes have applied thereto one set of complementary logic voltage levels for enabling said latch, said first inverter is enabled and said third is disabled, and when said clock input nodes have applied thereto a complementary set of logic voltage levels for not enabling said latch, said first inverter is disabled and said third inverter is enabled; said first inverter input node comprising said latch data input node; said first inverter output node comprising said latch complementary data output node and being connected to said second inverter input node; said second inverter output node comprising said latch data output node; and said third inverter being cross-coupled with said second inverter in a latching configuration, said third inverter input node being connected to said second inverter output node and said second inverter input node being connected to said third inverter output node.

Claim 3

A D-type latch in accordance with claim 1, wherein: said second inverter includes a complementary pair of insulated-gate field-effect transistors having gates connected in parallel and to said second inverter input node, and having respective conduction channels connected between respective ones of said pair of second inverter voltage supply nodes and said second inverter output node; and wherein: said first and third inverters each includes a complementary pair of insulated-gate field-effect transistors having gates connected in parallel and to the respective inverter input node, and having respective conduction channels, said first and third inverters each further including a pair of unidirectional conduction devices connected in series with respective ones of said complementary pair of transistors to define a pair of series circuits, and said series circuits being connected between respective ones of said pair of inverter voltage supply nodes and said inverter output node of the respective inverter.

Claim 4

A D-type latch in accordance with claim 2, wherein said unidirectional conduction devices of said first and third inverters are each connected between each of the series-connected transistors, respectively, of the respective inverter and the inverter output node of the respective inverter.

Claim 5

A D-type latch having a data input node, a data output node, and a complementary data output node, said latch comprising first, second and third inverters each having an input node, an output node, and a pair of inverter voltage supply nodes, each of said inverters including a complementary pair of insulated-gate field effect transistors each having a conduction channel and a gate electrode for controlling the conductance of the channel, said first and third inverters each further including a pair of unidirectional conduction elements, each of said inverters including first and second conduction paths, each conduction path connected between one of the pair of inverter voltage supply nodes of the particular inverter and the output node of the particular inverter, each of said paths included in said second inverter in turn including the conduction channel of one of the transistors of the pair included in said second inverter, each of said paths included in said first and third inverters in turn including the conduction channel of one of the transistors of the pair included in each of said first and third inverters in series with one of said unidirectional conduction elements with the unidirectional conduction elements of each pair poled oppositely with respect to the output node of the particular inverter such that the particular inverter is enabled with voltage polarity of one sense applied to its voltage supply nodes permitting conduction through either unidirectional conduction element, and such that the particular inverter is disabled with voltage polarity of the opposite sense applied to its voltage supply nodes preventing conduction through either unidirectional conduction element, and the gate electrodes of each transistor pair being electrically connected to the particular inverter input node; said second inverter voltage supply nodes comprising latch voltage supply nodes for continuously enabling said second inverter; said first and third inverter voltage supply nodes comprising complementary clock input nodes in a manner such that, when said clock input nodes have applied thereto one set of complementary logic voltage levels for enabling said latch, said first inverter is enabled and said third inverter is disabled, and when said clock input nodes have applied thereto a complementary set of logic voltage levels for not enabling said latch, said first inverter is disabled and said third inverter is enabled; said first inverter input node comprising said latch data input node; said first inverter output node comprising said latch complementary data output node and being connected to said second inverter input node; said second inverter output node comprising said latch data output node; and said third inverter being cross-coupled with said second inverter in a latching configuration, said third inverter input node being connected to said second inverter output node, and said second inverter input node being connected to said third inverter output node.

Claim 6

A D-type latch having a data input node, a data output node, and a complementary data output node, said latch comprising first, second and third inverters each having an input node, an output node, and a pair of inverter voltage supply nodes, each of said inverters including a complementary pair of insulated-gate field effect transistors each having a conduction channel and a gate electrode for controlling the conductance of the channel, said first and third inverters each further including a pair of unidirectional conduction elements, each of said inverters including first and second conduction paths, each conduction path connected between one of the pair of inverter voltage supply nodes of the particular inverter and the output node of the particular inverter, each of said paths included in said second inverter in turn including the conduction channel of one of the transistors of the pair included in said second inverter, each of said paths included in said first and third inverters in turn including the conduction channel of one of the transistors of the pair included in each of said first and third inverters in series with one of said unidirectional conduction elements with the unidirectional conduction elements of each pair poled oppositely with respect to the output node of the particular inverter such that the particular inverter is enabled with voltage polarity of one sense applied to its voltage supply nodes permitting conduction through either unidirectional conduction element, and such that the particular inverter is disabled with voltage polarity of the opposite sense applied to its voltage supply nodes preventing conduction through either unidirectional conduction element, and the gate electrodes of each transistor pair being electrically connected to the particular inverter input node; said second inverter voltage supply nodes comprising latch voltage supply nodes for continuously enabling said second inverter; said first and third inverter voltage supply nodes comprising complementary clock input nodes in a manner such that, when said clock input nodes have applied thereto one set of complementary logic voltage levels for enabling said latch, said first inverter is enabled and said third inverter is disabled, and when said clock input nodes have applied thereto a complementary set of logic voltage levels for not enabling said latch, said first inverter is disabled and said third inverter is enabled; said first inverter input node comprising said latch data input node; said first inverter output node comprising said latch complementary data output node and being connected to said second inverter input node; said second inverter output node comprising said latch data output node; and said third inverter being cross-coupled with said second inverter in a latching configuration, said third inverter input node being connected to said second inverter output node, and said second inverter input node being connected to said third inverter output node.

Claim 7

A D-type latch in accordance with claim 4, wherein said unidirectional conduction elements of said first and third inverters are each connected between the transistor conduction channel of each of the conduction paths, respectively, of the respective inverter and the inverter output node of the respective inverter.