US3716724A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Shift register incorporating complementary field effect transistors
Assignee: International Business Machines Corp
•
Filing: 1971-06-30
•
Granted: 1973-02-13
•
Expires: 1991-06-30
Abstract
Abstract An inverter incorporating a pair of complementary field effect transistors and a pair of Schottky barrier diodes disposed in series with the complementary transistors is disclosed. The gates of the complementary transistors are connected in parallel to a pulsed source which provides positive and negative inputs to the inverter. First and second pulsed sources are connected to the inverter which, during an ENABLE cycle, provide voltages of opposite polarity to the inverter which, operating in a common source mode, charges an output to one of the source potentials. During a DISABLE cycle, the potential at the output is locked at a node by applying to the inverter potentials complementary to those initially applied to the inverter. A shift register stage consisting of the arrangement just described and an inverted inverter is also disclosed. When this shift register stage is actuated, during the ENABLE portion of a given cycle, one inverter is enabled while the other is disabled and, during the DISABLE portion of the given cycle, the other inverter is enabled while the first inverter is disabled. Also included are embodiments which are operable in a static mode as well as a dynamic mode.
Inventors
- 👤 J Parrish
- 👤 D Spampinato
- 👤 L Terman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 13:31
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963; G; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184; G11C19/28
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
130 words
A shift register stage which shifts information from an input to an output during an enable and disable portion of a given cycle comprising: first and second complementary inverter circuits each including a pair of complementary field effect transistors the gates of which are connected in parallel and a pair of unidirectional devices disposed in series with said transistors said second inverter being reversed relative to said first inverter the output of said first inverter being connected to the input of said second inverter, means connected to said first and second inverters for one of enabling and disabling said inverters during said cycle one of said inverters being enabled while the other is disabled said unidirectional devices of each of said inverters being conductive when their associated inverter is enabled.
Claim 2
Dependent Claim
130 words
A shift register stage which shifts information from an input to an output during an enable and disable portion of a given cycle comprising: first and second complementary inverter circuits each including a pair of complementary field effect transistors the gates of which are connected in parallel and a pair of unidirectional devices disposed in series with said transistors said second inverter being reversed relative to said first inverter the output of said first inverter being connected to the input of said second inverter, means connected to said first and second inverters for one of enabling and disabling said inverters during said cycle one of said inverters being enabled while the other is disabled said unidirectional devices of each of said inverters being conductive when their associated inverter is enabled.
Claim 3
Dependent Claim
130 words
A shift register stage which shifts information from an input to an output during an enable and disable portion of a given cycle comprising: first and second complementary inverter circuits each including a pair of complementary field effect transistors the gates of which are connected in parallel and a pair of unidirectional devices disposed in series with said transistors said second inverter being reversed relative to said first inverter the output of said first inverter being connected to the input of said second inverter, means connected to said first and second inverters for one of enabling and disabling said inverters during said cycle one of said inverters being enabled while the other is disabled said unidirectional devices of each of said inverters being conductive when their associated inverter is enabled.
Claim 4
Dependent Claim
130 words
A shift register stage which shifts information from an input to an output during an enable and disable portion of a given cycle comprising: first and second complementary inverter circuits each including a pair of complementary field effect transistors the gates of which are connected in parallel and a pair of unidirectional devices disposed in series with said transistors said second inverter being reversed relative to said first inverter the output of said first inverter being connected to the input of said second inverter, means connected to said first and second inverters for one of enabling and disabling said inverters during said cycle one of said inverters being enabled while the other is disabled said unidirectional devices of each of said inverters being conductive when their associated inverter is enabled.
Claim 5
Dependent Claim
29 words
A shift register stage according to Claim 1 further including a pulsed voltage source which applies one of positive and negative potentials to said gates of said first inverter.
Claim 6
Dependent Claim
29 words
A shift register stage according to claim 1 further including a pulsed voltage source which applies one of positive and ground potentials to said gates of said first inverter.
Claim 7
Dependent Claim
29 words
A shift register stage according to claim 1 further including a pulsed voltage source which applies one of negative and ground potentials to said gates of said first inverter.
Claim 8
Dependent Claim
34 words
A shift register stage according to claim 1 further including means connected to said first and second inverters for maintaining statically the potentials at said input and output during a portion of said cycle.
Claim 9
Dependent Claim
14 words
A shift register stage according to claim 1 wherein said unidirection devices are diodes.
Claim 10
Dependent Claim
16 words
A shift register stage according to claim 1 wherein said unidirection devices are Schottky barrier diodes.
Claim 11
Dependent Claim
53 words
A shift register stage according to claim 1 wherein said means for one of enabling and disabling said inverter includes first and second pulsed sources which apply positive and negative potentials simultaneously to said inverters, the potentials applied during said disable portion being the complement of said potentials applied during said enable portion.
Claim 12
Dependent Claim
53 words
A shift register stage according to claim 1 wherein said means for one of enabling and disabling said inverter includes first and second pulsed sources which apply positive and ground potentials simultaneously to said inverters the potentials applied during said disable portion being the complement of said potentials applied during said enable portion.
Claim 13
Dependent Claim
53 words
A shift register stage according to claim 1 wherein said means for one of enabling and disabling said inverter includes first and second pulsed sources which apply negative and ground potentials simultaneously to said inverters, the potentials applied during said disable portion being the complement of said potentials applied during said enable portion.
Claim 14
Dependent Claim
18 words
A shift register stage according to claim 1 wherein said complementary field effect transistors are enhancement mode devices.
Claim 15
Dependent Claim
65 words
A shift register stage according to claim 5 wherein said means for maintaining includes, a third complementary inverter identical to said first inverter interposed between said first and second inverters and, means interconnecting the output of said third inverter and the input of said first inverter for feeding back the potential on the output of said third inverter to the input of said first inverter.
Claim 16
Dependent Claim
57 words
A shift register stage according to claim 12 wherein said interconnecting means includes a field effect transistor disposed between said output of said third inverter and said input of said first inverter, and a pulsed source connected to the gate of said field effect transistor operable during an enable portion of said cycle for said first inverter.
References Cited (Backward Citations)
US2910597A
Cited
US3431433A
Cited
US3454785A
Cited
US3322974A
Cited
US3588527A
Cited
US3588528A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-13 | 1976-08-14 | 1977-02-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-13 | 1980-08-14 | 1981-02-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-13 | 1984-08-14 | 1985-02-13 | $7700.00 | Window Closed / Lapsed |