Shift register employing insulated gate field effect transistors

Claim 1

A SHIFT REGISTER COMPRISING: A SEMICONDUCTOR BODY, A FIRST GROUP AND A SECOND GROUP FO FIELD EFFECT TRANSISTORS FORMED IN SAID BODY, EACH TRANSISTOR OF EACH GROUP MEANS FOR SUPPLYING AN INPUT SIGNAL TO THE GATE ELECTRODE OF A SECOND OF SAID TRANSISTORS OF SAID FIRST GROUP, MEANS ON SAID BODY FOR CONNECTING THE SOURCE ELECTRODE OF SAID FIRST TRANSISTOR OF SAID FIRST GROUP TO THE GATE ELECTRODE OF A SECOND OF SAID TRANSISTORS OF SAID SECOND GROUP SO AS TO CONNECT SAID SECOND GROUP OF TRANSISTORS IN CASCADE WITHSAID FIRST GROUP, MEANS FOR SUPPLYING A FIRST TRAIN OF SYNCHRONIZING PULSES TO THE GATE ELECTRODES OF THE TRANSISTORS OF SAID FIRST GROUP OTHER THAN SAID SECOND TRANSISTOR THEREOF, MEANS FOR SUPPLYING A SECOND TRAIN OF SYNCHRONIZING PULSES SIGNAL TO THE GATE ELECTRODES OF THE TRANSISTORS OF SAID SECOND GROUP OTHER THAN SAID SECOND TRANSISTOR THEREOF, SAID SECOND TRAIN OF SYNCHRONIZING PULSES BEING OUT OF TIME PHASE WITH SAID FIRST TRAIN OF SYNCHRONIZING PULSES, AND MEANS CONNECTED TO SAID SECOND GROUP OF TRANSISTORS FOR SUPPLYING AN OUTPUT SIGNAL REPRESENTATIVE OF A DELAYED VERSION OF SAID INPUT SIGNAL.