Patent US4517643A successfully refreshed from Google Patents.
US4517643A
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Interrupt control apparatus for a data processing system
Assignee: Toshiba Corp
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Filing: 1982-03-24
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Granted: 1985-05-14
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Expires: 2002-03-24
Abstract
Abstract A data processing system which include a central processing unit having a program counter, a main memory for storing a return instruction including the contents of the program counter and interrupting inhibiting information and for storing the contents of a general register in the CPU, interruption means for controlling the storage of the return instruction and the general register contents in the main memory upon occurrence of a first interruption, detection means for reading the return instruction stored in the main memory upon completion of the first interruption and for initiating the immediate occurrence of a second interruption in accordance with the inhibiting information of the return instruction read in the main memory, and return means for restoring the return instruction and the general register contents stored in the main memory to the central processing unit in the event that the detecting means determines that there is no further interruption to be accepted.
Inventors
- 👤 Akira Bannai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:44
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F8/00; G06F8/60; G06F8/65; G06F8/66; G06F9/461
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
322 words
A data processing apparatus, comprising: a central processing unit having a program counter and a general register; main memory means electrically connected to said CPU for storing data including a Program Status Word which includes the contents to said program counter and interruption inhibition information and wherein said main memory means stores the contents of said general register; interruption means for controlling the storage of said data in said main memory when said CPU is processing a main program at the same time a first interruption occurs including a means for conducting a PUSH operation including the storing of the Program Status Word in said main memory; means for processing a program associated with said first interruption; means for saving, in an auxiliary memory, said Program Status Word, from said main memory including interruption inhibition information and the contents of said program counter at the time of said first interruption; means for detecting an enabling second interruption including means for indicating that a second interruption has been made during the processing of said first interruption program and means for determining that the interruption inhibition information in the Program Status Word stored in said auxiliary memory indicates that said second interruption signal is enabling, while the CPU control is returning to said main program due to the execution of a return instruction after the processing of said first interruption program wherein said means for detecting outputs a detection signal when said second interruption signal has been made and when said second interruption signal has been made and is enabling; means for conducting a POP operation during the execution of a return instruction including means for restoring the Program Status Word to the CPU from said auxiliary memory; and control means responsive to said detection signal for inhibiting the operation of said means for conducting a POP operation and for making the CPU control advance to process a program associated with said second interruption.
Claim 2
Dependent Claim
322 words
A data processing apparatus, comprising: a central processing unit having a program counter and a general register; main memory means electrically connected to said CPU for storing data including a Program Status Word which includes the contents to said program counter and interruption inhibition information and wherein said main memory means stores the contents of said general register; interruption means for controlling the storage of said data in said main memory when said CPU is processing a main program at the same time a first interruption occurs including a means for conducting a PUSH operation including the storing of the Program Status Word in said main memory; means for processing a program associated with said first interruption; means for saving, in an auxiliary memory, said Program Status Word, from said main memory including interruption inhibition information and the contents of said program counter at the time of said first interruption; means for detecting an enabling second interruption including means for indicating that a second interruption has been made during the processing of said first interruption program and means for determining that the interruption inhibition information in the Program Status Word stored in said auxiliary memory indicates that said second interruption signal is enabling, while the CPU control is returning to said main program due to the execution of a return instruction after the processing of said first interruption program wherein said means for detecting outputs a detection signal when said second interruption signal has been made and when said second interruption signal has been made and is enabling; means for conducting a POP operation during the execution of a return instruction including means for restoring the Program Status Word to the CPU from said auxiliary memory; and control means responsive to said detection signal for inhibiting the operation of said means for conducting a POP operation and for making the CPU control advance to process a program associated with said second interruption.
Claim 3
Dependent Claim
127 words
A data processing apparatus according to claim 1, further comprising: interruption means for producing one of said first and second interruption including a priority control for establishing priority interruption levels; and wherein said interruption inhibiting information defines a priority interruption level necessary to produce an interruption and wherein said means for determining that the interruption inhibiting information in the program status word indicates the enabling of said second interruption includes a comparing means for determining whether the interruption level defined by said priority control of said interruption means has priority relative to said designating information of said interrupt inhibiting information in order to determine whether one of said first and said second interruptions is to be performed or said data is to be restored to said CPU.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-05-13 | 1988-11-12 | 1989-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-05-13 | 1992-11-12 | 1993-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-05-13 | 1996-11-12 | 1997-05-14 | $7700.00 | Window Closed / Lapsed |