Data processing device using a subroutine call instruction

Claim 2

A data processing device for executing a subroutine CALL instruction to CALL a subroutine, the CALL instruction including an operation code and a memory address to alter the sequence of program execution by setting a program counter of predetermined bit length to the address included in the CALL instruction, said data processing device comprising: an assembler for converting said operation code and said memory address into object code; a read only memory for storing instructions or data, said read only memory for selectively outputting said stored instructions or data; an instruction register connected to said read only memory for storing one of said instructions outputted from said read only memory; an instruction decoder connected to said instruction register for decoding said instruction stored in said instruction register to produce corresponding control signals; data converting means connected to said instruction register and said assembler for receiving said object code from said assembler and for converting said object code into an address with a bit length corresponding to said predetermined bit length of said program counter, said program counter being connected to said data converting means for storing said converted address; and a stack connected to said program counter for storing a return address of said called subroutine.

Claim 3

A data processing device according to claim 1, in which said data converting means comprises a mask ROM.

Claim 4

In a data processing device comprising: a program storing section for storing programs comprising instructions including a subroutine CALL instruction and for selectively outputting said instructions; an input/output section; an input/output unit; a first bus coupled to said input/output section and to said input/output unit for bidirectionally transferring information between said input/output section and said input/output unit, said input/output section for controlling the transfer of data on said bus; a data memory section connected to said input/output section via a second bus for storing data bidirectionally transferred between said input/output section and said input/output unit; control means connected to said program storing section, said data storing section, and said input/output section for decoding an instruction outputted from said program storing section to control said program storing section, said input/output section, and said data memory section; an operational section connected to said control means and said data storing section for performing arithmetic and logic operations in response to said control means, the improvement comprising said control means including: an instruction register connected to said program storing section for storing an instruction outputted from said program storing section said stored instruction including an address field for storing a coded address; an instruction decoder connected to said instruction register for decoding an instruction stored in said instruction register and for outputting said decoded instruction; data converting means connected to said instruction register for receiving said decoded instruction and for converting the said address in the address field of a received decoded instruction into an effective address; a program counter connected to said data converting means and said program storing section for storing said effective address to indicate the location wherein an instruction stored in said instruction register is stored in said program storing section; and a stack connected to said program counter for storing the return address of a subroutine call instruction when an instruction outputted from said instruction register is a said subroutine CALL instruction.

Claim 5

In a data processing device comprising: a program storing section for storing programs comprising instructions including a subroutine CALL instruction and for selectively outputting said instructions; an input/output section; an input/output unit; a first bus coupled to said input/output section and to said input/output unit for bidirectionally transferring information between said input/output section and said input/output unit, said input/output section for controlling the transfer of data on said bus; a data memory section connected to said input/output section via a second bus for storing data bidirectionally transferred between said input/output section and said input/output unit; control means connected to said program storing section, said data storing section, and said input/output section for decoding an instruction outputted from said program storing section to control said program storing section, said input/output section, and said data memory section; an operational section connected to said control means and said data storing section for performing arithmetic and logic operations in response to said control means, the improvement comprising said control means including: an instruction register connected to said program storing section for storing an instruction outputted from said program storing section said stored instruction including an address field for storing a coded address; an instruction decoder connected to said instruction register for decoding an instruction stored in said instruction register and for outputting said decoded instruction; data converting means connected to said instruction register for receiving said decoded instruction and for converting the said address in the address field of a received decoded instruction into an effective address; a program counter connected to said data converting means and said program storing section for storing said effective address to indicate the location wherein an instruction stored in said instruction register is stored in said program storing section; and a stack connected to said program counter for storing the return address of a subroutine call instruction when an instruction outputted from said instruction register is a said subroutine CALL instruction.

Claim 6

A data processing device according to claim 3, in which said data converting means includes a mask ROM.

Claim 7

A data processing device according to claim 4, in which an instruction with an address field to be inputted to said data converting means is a subroutine call instruction.

Claim 8

A data processing device comprising: a read only memory for storing a program portion including subroutine CALL instructions and other instructions, said read only memory for selectively outputting said instructions; an instruction register connected to said read only memory for storing an instruction outputted from said read only memory said stored instruction including an address field storing a coded address; an instruction decoder connected to said instruction register for decoding an instruction outputted from said instruction register to produce corresponding control data; decoder means connected to said instruction register for receiving said coded address of the address field of an instruction stored in said instruction register; a program counter connected to said decoder means and said instruction register for storing the address of a location stored in said read only memory; a stack connected to said program counter for storing the return address of a subroutine call instruction when an instruction from said instruction register is a said subroutine CALL instruction; an arithmetic/logic unit; a source bus connecting said arithmetic/logic unit to said read only memory and said instruction decoder, said arithmetic/logic unit for performing arithmetic operations and logic operations in response to said control data produced by said instruction decoder; a destination bus; a random access memory for storing data, said random access memory being connected to said read only memory, said instruction decoder, and said arithmetic/logic unit; a first register and a second register, said first register and said second register each connected to said source bus, said destination bus, and said random access memory, said first register and said second register for storing selected addresses in said random access memory; an accumulator connected to said source bus and said destination bus for use during said arithmetic operations and said logic operations; a register group for representing the results of said arithmetic operations and said logic operations, said register group being connected to said source bus, said destination bus and said arithmetic/logic unit; and an input/output control unit connected to said source bus and said destination bus for controlling data to be inputted to said source bus.

Claim 9

A data processing device comprising: a read only memory for storing a program portion including subroutine CALL instructions and other instructions, said read only memory for selectively outputting said instructions; an instruction register connected to said read only memory for storing an instruction outputted from said read only memory said stored instruction including an address field storing a coded address; an instruction decoder connected to said instruction register for decoding an instruction outputted from said instruction register to produce corresponding control data; decoder means connected to said instruction register for receiving said coded address of the address field of an instruction stored in said instruction register; a program counter connected to said decoder means and said instruction register for storing the address of a location stored in said read only memory; a stack connected to said program counter for storing the return address of a subroutine call instruction when an instruction from said instruction register is a said subroutine CALL instruction; an arithmetic/logic unit; a source bus connecting said arithmetic/logic unit to said read only memory and said instruction decoder, said arithmetic/logic unit for performing arithmetic operations and logic operations in response to said control data produced by said instruction decoder; a destination bus; a random access memory for storing data, said random access memory being connected to said read only memory, said instruction decoder, and said arithmetic/logic unit; a first register and a second register, said first register and said second register each connected to said source bus, said destination bus, and said random access memory, said first register and said second register for storing selected addresses in said random access memory; an accumulator connected to said source bus and said destination bus for use during said arithmetic operations and said logic operations; a register group for representing the results of said arithmetic operations and said logic operations, said register group being connected to said source bus, said destination bus and said arithmetic/logic unit; and an input/output control unit connected to said source bus and said destination bus for controlling data to be inputted to said source bus.

Claim 10

A data processing device according to claim 6, in which said decoder means includes a mask ROM.

Claim 11

A data processing device according to claim 6, in which an instruction with an address field to be inputted to said decoder means is a subroutine call instruction.