Data transfer system for a data processing system provided with direct memory access units

Claim 1

In a data processing system which includes a central processing unit with an n-bit word length, where n is a positive integer having a value greater than 7, a main memory, a plurality of direct memory access units and an n-bit data bus coupling the central processing unit, the main memory and the direct memory access units for transfer of data between the direct memory access units and the main memory, the improvement comprising a data transfer system for accessing the main memory, the data transfer system comprising: (a) said main memory being capable of storing n-bit full-words in byte units, each full-word made up of m bytes where n/m is the number of bits in one byte and said memory having a separate transfer enable input for each of said m bytes; (b) said direct memory access units comprising at least one first direct memory access unit which can receive and deliver n-bit full-words, and at least one second direct memory access unit which can receive and deliver n/2 bit half-words, since n/2 is an integer; (c) a plurality of gate circuits coupling the main memory and the data bus line; (d) first data transfer control means for controlling the gate circuits so that data transfer is achieved between the main memory and the first direct memory access unit, using n bits of the data bus line and an n-bit memory location when the first direct memory access unit has access to the main memory; (e) zone specifying means having m zone selection inputs from the Central Processing unit, one corresponding to each of said m bytes in said main memory and responsive to said zone selection inputs and a control output from said first data transfer control means indicative of data transfer between the main memory and the first direct memory access unit, for selectively providing at least one signal to said separate transfer enable inputs to enable, transfer of at least one byte of data between an n-bit memory location and said first direct memory access unit using a corresponding part of the n-bit data bus line and the first direct memory access unit whereby through use of said zone specifying means appropriate zones within an n-bit full-word or a half-word may be specified; and (f) second data transfer control means for controlling the gate circuits so that data transfer is achieved between the main memory and the second direct memory access unit, using n/2 bits of the data bus line and n/2 bits from an n bit memory location when the second direct memory access unit has access to the main memory.