US4004281A
Expired / Lapsed
US
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Microprocessor chip register bus structure
Assignee: Motorola Solutions Inc
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Filing: 1974-10-30
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Granted: 1977-01-18
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Expires: 1994-10-30
Abstract
Abstract A program register is coupled between a data bus N bits wide and an address bus N bits wide for storing the address of the current byte of a multi-byte instruction currently being executed. A counter is also coupled between the address bus and the data bus and is additionally coupled to a program register to allow loading of the counter contents into the program register independently of the status of the address bus. An auxiliary register is also coupled between the address bus and the data bus. The counter is updated every machine cycle during execution of the instruction, except for certain instructions during which the counter is inhibited to allow it to function as an auxiliary register, thereby storing the address of the next instruction. For certain instructions, the address bus is utilized for data transfers to or from the auxiliary register simultaneously with loading of the program register from the counter, depending on the type of instruction being executed. The address bus is divided into two sections, each N bits wide, one for transferring higher order address bits and the other for independently transferring lower order address bits. This architecture permits execution of many instructions in fewer machine cycles than was previously possible.
Inventors
- 👤 Thomas H. Bennett
- 👤 Anthony E. Kouvoussis
- 👤 Michael F. Wiles
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:20
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/342; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7832; G06F9/22; G06F9/26; G06F9/262; G06F9/32; G06F9/321; G06F9/355; G06F9/3557
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
250 words
In a microprocessor including an address bus coupled to an address output circuit and a data bus coupled to a data input-output circuit, said microprocessor being suitable for executing a plurality of instructions stored in a memory in accordance with a plurality of machine cycles, each of said instructions including an operational code, circuitry comprising: program register storage means coupled between said address bus and said data bus for storing an address of an operational code of a first instruction during a first machine cycle; said program register storage means including first means for transferring said address of said operational code to said address bus during said first machine cycle; incrementor means coupled between said address bus and said data bus for receiving an address from said data bus or said address bus in response to one of said instructions; said incrementor means including second means for transferring said address to said address bus during said first machine cycle in response to one of said instructions; said incrementor means also including third means for incrementing said address during said first machine cycle; said incrementor means also including fourth means for transferring said incremented address into said program register storage means during a second machine cycle; transfer bus means coupled between said program register storage means and said incrementor means for effecting said transfer of said incremented address; and control and timing circuitry coupled to said program register means and said incrementor means for effecting said first and second machine cycles.
Claim 2
Dependent Claim
250 words
In a microprocessor including an address bus coupled to an address output circuit and a data bus coupled to a data input-output circuit, said microprocessor being suitable for executing a plurality of instructions stored in a memory in accordance with a plurality of machine cycles, each of said instructions including an operational code, circuitry comprising: program register storage means coupled between said address bus and said data bus for storing an address of an operational code of a first instruction during a first machine cycle; said program register storage means including first means for transferring said address of said operational code to said address bus during said first machine cycle; incrementor means coupled between said address bus and said data bus for receiving an address from said data bus or said address bus in response to one of said instructions; said incrementor means including second means for transferring said address to said address bus during said first machine cycle in response to one of said instructions; said incrementor means also including third means for incrementing said address during said first machine cycle; said incrementor means also including fourth means for transferring said incremented address into said program register storage means during a second machine cycle; transfer bus means coupled between said program register storage means and said incrementor means for effecting said transfer of said incremented address; and control and timing circuitry coupled to said program register means and said incrementor means for effecting said first and second machine cycles.
Claim 3
Dependent Claim
24 words
The circuit as recited in claim 1 wherein said incrementor means further includes means for storing said incremented address during said second machine cycle.
Claim 4
Dependent Claim
34 words
The circuitry as recited in claim 1 wherein the data bus is coupled to an input of said address output circuit for transferring data on said data bus directly to said address output circuit.
Claim 5
Dependent Claim
16 words
The circuitry as recited in claim 1 wherein said microprocessor is an N-channel MOS semiconductor chip.
Claim 6
Dependent Claim
239 words
In a microprocessor including an address bus coupled to an address output circuit and a data bus coupled to a data input-output circuit, said microprocessor being suitable for executing a plurality of instructions stored in a memory in accordance with a plurality of machine cycles each having first and second time frames thereof, respectively, each of said instructions including an operational code, circuitry comprising: program register means coupled between said address bus and said data bus for storing an address of an operational code of a first instruction during a first machine cycle, said program register means including means for fetching said operational code from a location in said memory corresponding to said address, during a first time frame of said first machine cycle; counter means coupled between said address bus and data bus for incrementing or decrementing its own contents in response to a current instruction, during a second time frame of said first machine cycle, said counter means including means for transferring said incremented or decremented contents into said program register means during a first time frame of a second machine cycle; transfer bus means coupled between said program register means and said counter means for effecting said transfer of said incremented or decremented contents independently of said address bus and said data bus; and control and timing circuitry coupled to said program register means and said counter means for effecting said first and second machine cycles.
Claim 7
Dependent Claim
239 words
In a microprocessor including an address bus coupled to an address output circuit and a data bus coupled to a data input-output circuit, said microprocessor being suitable for executing a plurality of instructions stored in a memory in accordance with a plurality of machine cycles each having first and second time frames thereof, respectively, each of said instructions including an operational code, circuitry comprising: program register means coupled between said address bus and said data bus for storing an address of an operational code of a first instruction during a first machine cycle, said program register means including means for fetching said operational code from a location in said memory corresponding to said address, during a first time frame of said first machine cycle; counter means coupled between said address bus and data bus for incrementing or decrementing its own contents in response to a current instruction, during a second time frame of said first machine cycle, said counter means including means for transferring said incremented or decremented contents into said program register means during a first time frame of a second machine cycle; transfer bus means coupled between said program register means and said counter means for effecting said transfer of said incremented or decremented contents independently of said address bus and said data bus; and control and timing circuitry coupled to said program register means and said counter means for effecting said first and second machine cycles.
Claim 8
Independent Claim
182 words
A method of operating a microprocessor including an address bus coupled to an address output circuit and a data bus coupled to a data input-output circuit and including program register means coupled between sid address bus and said data bus comprising the following steps: storing an address of an operational code of a first instruction in said program register means during a first machine cycle said address being obtained from an incrementer means coupled between said address bus and said data bus; fetching said operational code during a first time frame of said first machine cycle by transferring said address from said program register to said address bus and accessing a location of an external memory corresponding to said address; and loading said address in said incrementer means coupled between said address bus and said data bus; incrementing said address in said incrementer means during a second time frame of said first machine cycle; transferring said incremented address into said program register means during a first time frame of a second machine cycle independently of said address bus and said data bus.
Claim 9
Independent Claim
182 words
A method of operating a microprocessor including an address bus coupled to an address output circuit and a data bus coupled to a data input-output circuit and including program register means coupled between sid address bus and said data bus comprising the following steps: storing an address of an operational code of a first instruction in said program register means during a first machine cycle said address being obtained from an incrementer means coupled between said address bus and said data bus; fetching said operational code during a first time frame of said first machine cycle by transferring said address from said program register to said address bus and accessing a location of an external memory corresponding to said address; and loading said address in said incrementer means coupled between said address bus and said data bus; incrementing said address in said incrementer means during a second time frame of said first machine cycle; transferring said incremented address into said program register means during a first time frame of a second machine cycle independently of said address bus and said data bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-01-18 | 1980-07-19 | 1981-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-01-18 | 1984-07-19 | 1985-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-01-18 | 1988-07-19 | 1989-01-18 | $7700.00 | Window Closed / Lapsed |