US4509250A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for manufacturing a monolithic integrated circuit comprising at least one bipolar planar transistor
Assignee: ITT Inc
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Filing: 1983-09-09
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Granted: 1985-04-09
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Expires: 2003-09-09
Abstract
Abstract In the process according to the invention, in addition to the conventional two photoresist processes for opening the contact holes and for manufacturing the interconnecting pattern, two photoresist processes are used with one photoresist mask each for manufacturing the regions of the planar transistor. Without additional photoresist masks, further semiconductor components, such as integrated resistors and/or lateral transistors are capable of being manufactured. The process is characterized by the fact that, the first photoresist mask is used to manufacture a diffusion masking layer which leaves the base area of the planar transistor unmasked. In this area, the dopings of the collector region are introduced into the substrate and the collector region is diffused. Thereafter, at a relatively small dose rate, there is carried out an implantation of dopings of the base region. Upon removal of the diffusion masking layer and by employing a second photoresist mask, an oxidation masking layer is deposited which covers both the rim portion of the collector region and the emitter area. The oxidation masking layer serves as an implantation mask for the dopings of the external base partial region and for manufacturing an implantation mask of a thermally produced silicon oxide. Through the openings in this implantation mask there is effected the implantation of the dopings of the emitter region and those of the collector connecting region.
Inventors
- 👤 Lothar Blossfeld
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:28
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/20; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10D84/611; H10D84/613; H10D84/615
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
351 words
A process for manufacturing a monolithic integrated circuit comprising at least one bipolar vertical planar transistor whose emitter region is formed in one surface of a semiconducting substrate into a base region which is diffused into a collector region, said process employing a first photoresist mask to produce a diffusion masking layer whereby a collector area is restricted, dopings of a conductivity type of the collector region being implanted and diffused into said collector area; then employing a second photoresist mask, such that a base area is restricted and dopings of an base region are implanted; thereafter implanting the dopings of the emitter region into the emitter area; and employing a third photoresist mask to produce, contact holes in an insulated layer covering the surface side, and a fourth mask to produce an interconnection pattern on the insulating layer contacting the regions, characterized by the following processing steps: (a) employing said first photoresist mask to produce a diffusion masking layer on the surface side of the substrate which leaves the base area on the substrate unmasked; thereafter (b) introducing and diffusing the doping material of the collector region into the semiconductor surface within the base area, and subsequently introducing the doping material of the base region in a first relatively small dose into the semiconductor surface by way of ion implantation and by employing the diffusion masking layer as the implantation masking; thereafter (c) removing the diffusion masking layer and employing a second photoresist mask to produce an oxidation masking layer on the semiconductor surface, said oxidation masking layer covering both the emitter area and the base rim portion in a frame-shaped manner; thereafter (d) by employing the oxidation masking layer as an implantation mask, implanting ions of the base region type into the exposed semiconductor surface with a second relatively high dose rate, and subsequently thereto, thermal oxidizing the exposed semiconductor surface by forming a new implantation mask, in the course of which the implanted ions are activated; and (e) opening contact holes by employing a third photoresist mask and producing an interconnection pattern by employing a fourth photoresist mask.
Claim 2
Dependent Claim
351 words
A process for manufacturing a monolithic integrated circuit comprising at least one bipolar vertical planar transistor whose emitter region is formed in one surface of a semiconducting substrate into a base region which is diffused into a collector region, said process employing a first photoresist mask to produce a diffusion masking layer whereby a collector area is restricted, dopings of a conductivity type of the collector region being implanted and diffused into said collector area; then employing a second photoresist mask, such that a base area is restricted and dopings of an base region are implanted; thereafter implanting the dopings of the emitter region into the emitter area; and employing a third photoresist mask to produce, contact holes in an insulated layer covering the surface side, and a fourth mask to produce an interconnection pattern on the insulating layer contacting the regions, characterized by the following processing steps: (a) employing said first photoresist mask to produce a diffusion masking layer on the surface side of the substrate which leaves the base area on the substrate unmasked; thereafter (b) introducing and diffusing the doping material of the collector region into the semiconductor surface within the base area, and subsequently introducing the doping material of the base region in a first relatively small dose into the semiconductor surface by way of ion implantation and by employing the diffusion masking layer as the implantation masking; thereafter (c) removing the diffusion masking layer and employing a second photoresist mask to produce an oxidation masking layer on the semiconductor surface, said oxidation masking layer covering both the emitter area and the base rim portion in a frame-shaped manner; thereafter (d) by employing the oxidation masking layer as an implantation mask, implanting ions of the base region type into the exposed semiconductor surface with a second relatively high dose rate, and subsequently thereto, thermal oxidizing the exposed semiconductor surface by forming a new implantation mask, in the course of which the implanted ions are activated; and (e) opening contact holes by employing a third photoresist mask and producing an interconnection pattern by employing a fourth photoresist mask.
Claim 3
Dependent Claim
106 words
A process in accordance with claim 1, characterized in that for manufacturing an integrated resistor: during the processing step (a), said diffusion masking layer produced by employing said first photoresist mask leaves unmasked on said substrate the area of a resistor region; during processing step (b), the doping material of a resistor region is introduced into the semiconductor surface by employing said diffusion masking layer as an implantation mask; and during the processing step (c), said second photoresist mask is employed to produce an oxidation masking layer whch covers the marginal or rim portion of the region area at the contacting areas of the resistor region.
Claim 4
Dependent Claim
189 words
A process in accordance with claim 1, characterized in that for manufacturing an integrated lateral planar transistor: during processing step (a), said diffusion masking layer leaves the base area of said lateral planar transistor unmasked on the semiconductor surface, with the exception of web-shaped portions between the emitter region and the collector region, said portions being covered by web-shaped diffusion masking layer portions having a width such that, during processing step (b), the doping material of the conductivity type of the collector region of said vertical planar transistor forms a continuous base region of the lateral transistor during the diffusion of the collector region of said vertical planar transistor; during processing step (c), following the removal of the diffusion masking layer and said diffusion masking layer portions, said oxidation masking layer which is produced covers the base rim portions of said lateral transistor and the contacting area of the base region thereof; and during processing step (e) said contact holes of said lateral transistor are opened by employing the third photoresist mask and the interconnection pattern required for the lateral transistor is produced by employing the fourth photoresist mask.
Claim 5
Dependent Claim
189 words
A process in accordance with claim 2, characterized in that for manufacturing an integrated lateral planar transistor: during processing step (a), said diffusion masking layer leaves the base area of said lateral planar transistor unmasked on the semiconductor surface, with the exception of web-shaped portions between the emitter region and the collector region, said portions being covered by web-shaped diffusion masking layer portions having a width such that, during processing step (b), the doping material of the conductivity type of the collector region of said vertical planar transistor forms a continuous base region of the lateral transistor during the diffusion of the collector region of said vertical planar transistor; during processing step (c), following the removal of the diffusion masking layer and said diffusion masking layer portions, said oxidation masking layer which is produced covers the base rim portions of said lateral transistor and the contacting area of the base region thereof; and during processing step (e) said contact holes of said lateral transistor are opened by employing the third photoresist mask and the interconnection pattern required for the lateral transistor is produced by employing the fourth photoresist mask.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-04-08 | 1988-10-08 | 1989-04-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-04-08 | 1992-10-08 | 1993-04-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-04-08 | 1996-10-08 | 1997-04-09 | $7700.00 | Window Closed / Lapsed |