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US4507757A
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Avalanche fuse element in programmable memory
Assignee: Texas Instruments Inc
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Filing: 1982-03-23
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Granted: 1985-03-26
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Expires: 2002-03-23
Abstract
Abstract A programmable device is provided by a thin-oxide avalanche fuse element which is programmed at a voltage below the oxide breakdown level. This device may be used in a memory array of the PROM type. Upon breakdown, the thin oxide is perforated by small holes which fill with silicon to create short circuit.
Inventors
- 👤 David J. McElroy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 05:18
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
98 words
An electrically programmable semiconductor device comprising: a transistor having a source-to-drain path and a gate, and means for selectively activating the gate of the transistor for a sense operation, the source-to-drain path connected between a sense node and an access node, a thin dielectric separating the sense node from a common node, means for applying a high voltage to the sense node for selectively breaking down said dielectric due to an avalanche-mode current in said source-to-drain path to create an electrical short through said dielectric, the high voltage being less than the dielectric-breakdown voltage of said thin dielectric.
Claim 2
Dependent Claim
98 words
An electrically programmable semiconductor device comprising: a transistor having a source-to-drain path and a gate, and means for selectively activating the gate of the transistor for a sense operation, the source-to-drain path connected between a sense node and an access node, a thin dielectric separating the sense node from a common node, means for applying a high voltage to the sense node for selectively breaking down said dielectric due to an avalanche-mode current in said source-to-drain path to create an electrical short through said dielectric, the high voltage being less than the dielectric-breakdown voltage of said thin dielectric.
Claim 3
Dependent Claim
26 words
A device according to claim 1 wherein the transistor is an insulated-gate field-effect transistor activated for sense operation by a logic voltage on the gate thereof.
Claim 4
Dependent Claim
118 words
An electrically programmable semiconductor device comprising: a transistor having a source-to-drain path and a gate, and means for selectively activating the gate of the transistor for a sense operation, the source-to-drain path connected between a sense node and an access node, a thin dielectric separating the sense node from a common node, means for applying a high voltage to the sense node for selectively breaking down the dielectric in an avalanche mode to create an electrical short, the high voltage being less than the dielectric-breakdown voltage of the thin dielectric, wherein said common node is a conductor overlying a face of a semiconductor body, and the sense node is a region in said face partially underlying said conductor.
Claim 5
Dependent Claim
118 words
An electrically programmable semiconductor device comprising: a transistor having a source-to-drain path and a gate, and means for selectively activating the gate of the transistor for a sense operation, the source-to-drain path connected between a sense node and an access node, a thin dielectric separating the sense node from a common node, means for applying a high voltage to the sense node for selectively breaking down the dielectric in an avalanche mode to create an electrical short, the high voltage being less than the dielectric-breakdown voltage of the thin dielectric, wherein said common node is a conductor overlying a face of a semiconductor body, and the sense node is a region in said face partially underlying said conductor.
Claim 6
Dependent Claim
14 words
A cell according to claim 1 wherein the conductor is connected to reference potential.
Claim 7
Dependent Claim
98 words
An avalanche-mode fuse element comprising field-effect type transistor means including source and drain regions in a face of a semiconductor body and a gate overlying the face between the source and drain regions, a thin-oxide break-down area between the gate and the face adjacent the drain region, and means for applying voltages to the source, drain and gate to break down said thin-oxide area by avalanche-mode current between said source-drain regions to create an electrical short between said gate and drain region, wherein the voltage across said thin-oxide break-down area is less than the dielectric breakdown voltage thereof.
Claim 8
Dependent Claim
98 words
An avalanche-mode fuse element comprising field-effect type transistor means including source and drain regions in a face of a semiconductor body and a gate overlying the face between the source and drain regions, a thin-oxide break-down area between the gate and the face adjacent the drain region, and means for applying voltages to the source, drain and gate to break down said thin-oxide area by avalanche-mode current between said source-drain regions to create an electrical short between said gate and drain region, wherein the voltage across said thin-oxide break-down area is less than the dielectric breakdown voltage thereof.
Claim 9
Dependent Claim
30 words
A fuse element according to claim 5 wherein said dielectric breakdown voltage is in excess of 30 v. and the voltage creating said electrical short is less than 25 v.
Claim 10
Dependent Claim
104 words
A semiconductor read-only memory device comprising: an array of rows and columns of memory cells at a face of a semiconductor body, with row lines and column lines extending along said face, each of said cells including an access transistor and a storage element, the access transistor having a gate connected to a row line and having a source-drain path connecting a column line to a cell node, the storage element in each cell being connected between the cell node and a common node, and including a dielectric exhibiting a breakdown characteristic in response to programming voltage selectively applied to row and column lines.
Claim 11
Dependent Claim
104 words
A semiconductor read-only memory device comprising: an array of rows and columns of memory cells at a face of a semiconductor body, with row lines and column lines extending along said face, each of said cells including an access transistor and a storage element, the access transistor having a gate connected to a row line and having a source-drain path connecting a column line to a cell node, the storage element in each cell being connected between the cell node and a common node, and including a dielectric exhibiting a breakdown characteristic in response to programming voltage selectively applied to row and column lines.
Claim 12
Dependent Claim
123 words
A semiconductor read-only memory device comprising: an array of rows and columns of memory cells at a face of a semiconductor body, with row lines and column lines extending along said face, each of said cells including an access transistor and a storage element, the access transistor having a gate connected to a row line and having a source-drain path connecting a column line to a cell node, the storage element in each cell being connected between the cell node and a common node, and including a dielectric exhibiting a breakdown characteristic in response to programming voltage selectively applied to row and column lines, wherein the common node is a conductor extending along the face and separated from the face by said dielectric.
Claim 13
Dependent Claim
123 words
A semiconductor read-only memory device comprising: an array of rows and columns of memory cells at a face of a semiconductor body, with row lines and column lines extending along said face, each of said cells including an access transistor and a storage element, the access transistor having a gate connected to a row line and having a source-drain path connecting a column line to a cell node, the storage element in each cell being connected between the cell node and a common node, and including a dielectric exhibiting a breakdown characteristic in response to programming voltage selectively applied to row and column lines, wherein the common node is a conductor extending along the face and separated from the face by said dielectric.
Claim 14
Dependent Claim
29 words
A device according to claim 8 wherein a plurality of adjacent cells share a common node, the cell nodes for said adjacent cells being separate regions in said face.
Claim 15
Dependent Claim
26 words
A device according to claim 9 wherein the gates of the access transistors are separated from the face by a gate insulator thicker than said dielectric.
Claim 16
Dependent Claim
37 words
A device according to claim 10 wherein the access transistor has a gate voltage for read operations much less than said programming voltage, and said programming voltage is less than the dielectric breakdown voltage of said dielectric.
Claim 17
Dependent Claim
72 words
A semiconductor memory cell comprising: an access transistor connecting a sense node to an access line, and means for selectively activating the access transistor for read operation, a thin dielectric separating the sense node from a common node, means for applying a high voltage to the sense node for selectively breaking down the dielectric to create an electrical short, the high voltage being less than the dielectric-breakdown voltage of the thin dielectric.
Claim 18
Dependent Claim
72 words
A semiconductor memory cell comprising: an access transistor connecting a sense node to an access line, and means for selectively activating the access transistor for read operation, a thin dielectric separating the sense node from a common node, means for applying a high voltage to the sense node for selectively breaking down the dielectric to create an electrical short, the high voltage being less than the dielectric-breakdown voltage of the thin dielectric.
Claim 19
Dependent Claim
27 words
A cell according to claim 12 wherein the access transistor is an insulated-gate field-effect transistor activated for read operations by a logic voltage on the gate thereof.
Claim 20
Dependent Claim
100 words
A semiconductor memory cell comprising: an access transistor connecting a sense node to an access line, and means for selectively activating the access transistor for read operation, a thin dielectric separating the sense node from a common node, means for applying a high voltage to the sense node for selectively breaking down the dielectric to create an electrical short, the high voltage being less than the dielectric-breakdown voltage of the thin dielectric, wherein said common node is a conductor overlying a face of a semiconductor body, and the sense node is a region in said face partially underlying said conductor.
Claim 21
Dependent Claim
100 words
A semiconductor memory cell comprising: an access transistor connecting a sense node to an access line, and means for selectively activating the access transistor for read operation, a thin dielectric separating the sense node from a common node, means for applying a high voltage to the sense node for selectively breaking down the dielectric to create an electrical short, the high voltage being less than the dielectric-breakdown voltage of the thin dielectric, wherein said common node is a conductor overlying a face of a semiconductor body, and the sense node is a region in said face partially underlying said conductor.
Claim 22
Dependent Claim
14 words
A cell according to claim 14 wherein the conductor is connected to reference potential.
Claim 23
Dependent Claim
27 words
A cell according to claim 15 wherein the access transistor is an insulated-gate field-effect transistor activated for read operations by a logic voltage on the gate thereof.
Claim 24
Dependent Claim
17 words
A cell according to claim 16 wherein the logic voltage is much less than said high voltage.
Claim 25
Dependent Claim
21 words
A cell according to claim 16 wherein the gate oxide of said transistor is of greater thickness than said thin dielectric.
Claim 26
Independent Claim
142 words
A method of making a semiconductor memory cell of the programmed read-only type comprising the steps of: applying a layer of conductive material on a face of a body of semiconductor material, and patterning the layer to form a transistor gate and a program-element gate overlying and separated from a transistor area and a program-element by thin insulator, forming heavily-doped regions in said face adjacent said transistor and program-element areas, applying an insulator coating on said face over said layer, forming openings in said insulator coating over some of said heavily-doped regions, applying conductive strips on said face over said coating and extending into said openings to form connections to the heavily-doped regions, and selectively applying a voltage to said conductive strips at a level less than the dielectric breakdown of said thin insulator to create electric short at the program element.
Claim 27
Independent Claim
142 words
A method of making a semiconductor memory cell of the programmed read-only type comprising the steps of: applying a layer of conductive material on a face of a body of semiconductor material, and patterning the layer to form a transistor gate and a program-element gate overlying and separated from a transistor area and a program-element by thin insulator, forming heavily-doped regions in said face adjacent said transistor and program-element areas, applying an insulator coating on said face over said layer, forming openings in said insulator coating over some of said heavily-doped regions, applying conductive strips on said face over said coating and extending into said openings to form connections to the heavily-doped regions, and selectively applying a voltage to said conductive strips at a level less than the dielectric breakdown of said thin insulator to create electric short at the program element.
Claim 28
Dependent Claim
26 words
A method according to claim 19 wherein the semiconductor body is P-type silicon, the heavily doped region is N+, and the conductive material is polycrystalline silicon.
Claim 29
Dependent Claim
25 words
A method according to claim 20 wherein said conductive strips are metal and said coating separates said metal from said face except at said openings.
Claim 30
Dependent Claim
49 words
A method according to claim 21 wherein a coating of thick thermal field oxide is formed on said face before applying said layer, except in the transistor and program-element areas and what will be the heavily doped regions, and wherein said openings are laterally spaced from said field oxide.
Claim 31
Dependent Claim
71 words
A method according to claim 19 wherein an array of rows and columns of said cells is formed simultaneously at said face, and the metal includes a plurality of parallel strips of metal connecting to the drains of transistors for a plurality of cells in a column, and the conductor material is in strips connecting to the gates of transistors and program elements for a plurality of cells in a row.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-03-25 | 1988-09-24 | 1989-03-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-03-25 | 1992-09-24 | 1993-03-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-03-25 | 1996-09-24 | 1997-03-26 | $7700.00 | Window Closed / Lapsed |