US3668655A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Write once/read only semiconductor memory array
Assignee: Cogar Corp
•
Filing: 1970-03-26
•
Granted: 1972-06-06
•
Expires: 1990-03-26
Abstract
Abstract This disclosure relates to a write once/read only semiconductor memory array which utilizes a single voltage (above the memory cell breakdown voltage) on a word drive line to effect writing into any selected memory cell of the array. Each memory cell of the array is preferably provided with a protective diode connected in parallel to the cell to prevent breakdown of unselected memory cells.
Inventors
- 👤 Charles A Allen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 04:55
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/16; G11C17/06
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
196 words
A memory array comprising, in combination, a plurality of semiconductor memory cells interconnected to provide a memory array, each of said cells having a first electrical state prior to receiving a writing voltage signal and an irreversible different second electrical state after receiving a writing voltage signal; writing means electrically connected to said cells of said memory array for applying balancing write voltage signals to each end of said cells, each of said write voltage signals applied to the ends of said cells being at least equal to the voltage signal needed to place one of said memory cells into said second electrical state, said writing means comprises word driver means for changing the voltage signal applied to one end of selected memory cells and for causing a write voltage signal to be applied to the other end of selected memory cells and placing said selected memory cells in said second electrical state, reading means for sensing the information contained in said memory array, and protection means for preventing unselected memory cells from being accidentally placed into said second electrical state, said protection means comprises a diode connected in parallel to each of said memory cells.
Claim 2
Dependent Claim
196 words
A memory array comprising, in combination, a plurality of semiconductor memory cells interconnected to provide a memory array, each of said cells having a first electrical state prior to receiving a writing voltage signal and an irreversible different second electrical state after receiving a writing voltage signal; writing means electrically connected to said cells of said memory array for applying balancing write voltage signals to each end of said cells, each of said write voltage signals applied to the ends of said cells being at least equal to the voltage signal needed to place one of said memory cells into said second electrical state, said writing means comprises word driver means for changing the voltage signal applied to one end of selected memory cells and for causing a write voltage signal to be applied to the other end of selected memory cells and placing said selected memory cells in said second electrical state, reading means for sensing the information contained in said memory array, and protection means for preventing unselected memory cells from being accidentally placed into said second electrical state, said protection means comprises a diode connected in parallel to each of said memory cells.
Claim 3
Dependent Claim
126 words
A memory array in accordance with claim 1 wherein said writing means comprises word driver means for applying said write signal to only one end of said selected memory cell, said word driver means comprises a transistor, said word driver means further comprises a resistor connected to the collector of said transistor and connectable to a first voltage source whose value is sufficient to place said selected memory cell in said second electrical state, the base of said transistor being connectable to a second voltage source capable of turning on said transistor, and the emitter of said transistor being connected to ground, said one end of said selected memory cell being connected between said resistor and the collector of said transistor of said word driver means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-06-06 | 1975-12-06 | 1976-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-06-06 | 1979-12-06 | 1980-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-06-06 | 1983-12-06 | 1984-06-06 | $7700.00 | Window Closed / Lapsed |