NAND Logic gate circuit having improved response time

Claim 2

A NAND logic gate circuit comprising first and second terminals for connection to a power supply, a first transistor having a first main electrode coupled to said first terminal, a second main electrode coupled to said second terminal, and a control electrode for receiving a first input signal and generating a first output signal at said first main electrode, a second transistor having a first main electrode coupled to said first terminal, a second main electrode coupled to said second terminal, and a control electrode for receiving a second input signal and generating a second output signal at said first main electrode of said second transistor, an inverter transistor having a first main electrode, a second main electrode coupled to said second terminal, and a control electrode coupled to said first main electrode of said first transistor for receiving said first output signal, said inverter transistor providing a inverted first output signal at its first main electrode, logic gate means having an output terminal and receiving said second output signal and said first inverted output signal for generating a logical AND output signal on said output terminal; a third transistor having a first main electrode coupled to said first main electrode of said first transistor, a second main electrode coupled to said second terminal, and a control electrode responsive to said second input signal having a low value to change said first output signal to a low value independent of the value of said first input signal.

Claim 3

A NAND logic gate circuit according to claim 1 wherein said second input signal is applied to said control electrode of said third transistor.

Claim 4

In a NAND logic gate circuit comprising: an inverter circuit comprised of a first gate input circuit including a first PNP transistor having a base connected to a first input terminal; a collector connected to a ground terminal, and an emitter connected to a power supply terminal via a first resistor, and a first output circuit including a first NPN transistor having a base connected to an output of said first gate input circuit; an emitter connected to said ground terminal, and a collector connected to said power supply terminal via a second resistor and a NAND circuit comprised of a second gate input circuit including a second PNP transistor having a base connected to a second input terminal, a collector connected to said ground terminal, and an emitter connected to said power supply terminal via a third resistor, a second output circuit including a second NPN transistor having a base, a collector connected to an output terminal and an emitter connected to said ground terminal, a phase split stage circuit including a third NPN transistor having an emitter connected to said base of said second NPN transistor, a collector connected to said power supply terminal via a fourth resistor; and a base connected to an output of said second gate input circuit and to an output of said inverter circuit, and an off buffer circuit including at least a fourth NPN transistor having a base connected to the collector of said third NPN transistor, a collector connected to said power supply terminal via a fifth resistor, and an emitter connected to said output terminal, the improvement wherein a third PNP transistor having an emitter connected to said emitter of said first PNP transistor, a base connected to said second input terminal, and a collector connected to said ground terminal, and wherein said collector of said first NPN transistor is disconnected from said second resistor and said power supply terminal and is connected directly to the base of said third NPN transistor thereby decreasing the amount of electric current which flows out to said second input terminal from said inverter circuit when said first input terminal is in a high level and said second input terminal is in a low level.

Claim 5

In a NAND logic gate circuit comprising: an inverter circuit comprised of a first gate input circuit including a first PNP transistor having a base connected to a first input terminal; a collector connected to a ground terminal, and an emitter connected to a power supply terminal via a first resistor, and a first output circuit including a first NPN transistor having a base connected to an output of said first gate input circuit; an emitter connected to said ground terminal, and a collector connected to said power supply terminal via a second resistor and a NAND circuit comprised of a second gate input circuit including a second PNP transistor having a base connected to a second input terminal, a collector connected to said ground terminal, and an emitter connected to said power supply terminal via a third resistor, a second output circuit including a second NPN transistor having a base, a collector connected to an output terminal and an emitter connected to said ground terminal, a phase split stage circuit including a third NPN transistor having an emitter connected to said base of said second NPN transistor, a collector connected to said power supply terminal via a fourth resistor; and a base connected to an output of said second gate input circuit and to an output of said inverter circuit, and an off buffer circuit including at least a fourth NPN transistor having a base connected to the collector of said third NPN transistor, a collector connected to said power supply terminal via a fifth resistor, and an emitter connected to said output terminal, the improvement wherein a third PNP transistor having an emitter connected to said emitter of said first PNP transistor, a base connected to said second input terminal, and a collector connected to said ground terminal, and wherein said collector of said first NPN transistor is disconnected from said second resistor and said power supply terminal and is connected directly to the base of said third NPN transistor thereby decreasing the amount of electric current which flows out to said second input terminal from said inverter circuit when said first input terminal is in a high level and said second input terminal is in a low level.

Claim 6

A NAND logic gate circuit according to claim 3 wherein a PN junction diode is connected between the emitter of said first NPN transistor and said ground terminal.

Claim 7

A NAND logic gate circuit according to claim 3 which is integrated wherein said second PNP transistor and said third PNP transistor are formed within one and the same isolated region.