Low power clock generator

Claim 2

A clock generator circuit for producing an output clock signal having levels determined by positive and negative power supply levels in response to an input clock signal having levels determined by said positive power supply level and a ground level, comprising: an output transistor pair having conductive channels coupled in series between said positive power supply level and said negative power supply level; a final drive transistor pair having channels coupled in series between said positive power supply level and said negative power supply level, gates of the transistors of said final drive transistor pair being coupled to gates of corresponding ones of the transistors of said output transistor pair; a bootstrap capacitor coupled between a first node at the commonly coupled gates of one transistor of said output transistor pair and the corresponding transistor of said drive transistor pair, and a second node between said channels of said output transistor pair; an inverter transistor having a channel coupled between said negative power supply level and a third node at the commonly coupled gates of the other transistor of said output transistor pair and the corresponding transistor of said drive transistor pair, and a gate coupled to said first node; means for grounding said second node in response to said input clock signal going to said positive power supply level from said ground level until said inverter transistor is switched into its conducting state in response to charging of said bootstrap capacitor; and means for discharging said first node to said negative power supply level in response to said input clock signal going from said positive power supply level to said ground level.

Claim 3

The clock generator circuit of claim 1, wherein all of said transistors are FET devices having a single common gate oxide layer.

Claim 4

The clock generator circuit of claim 2, wherein said means for grounding said second node comprises a third transistor pair having channels coupled in series between said positive power supply level and ground, a junction point between said transistors of said third pair being coupled to said third node and a gate of one transistor of said third pair receiving said input clock signal; and means for inverting said input clock signal, the inverted clock signal being applied to a gate and drain of the other transistor of said third pair.

Claim 5

The clock generator circuit of claim 3, wherein said means for discharging said first node comprises an eighth transistor having a channel coupled between said first node and said negative power supply level; and level-shifting circuit means operating in response to said input clock signal and said inverted clock signal for applying said negative power supply level to the gate of said eighth transistor in response to said input clock signal going to said ground level.

Claim 6

The clock generator circuit of claim 4, wherein said level-shifting circuit means comprises ninth through twelfth transistors, said ninth and tenth transistors having channels coupled in series between said input clock signal and said negative power supply level, said input clock signal being applied to a gate of said ninth transistor and said inverted clock signal being applied to a gate of said tenth transistor, said eleventh and twelfth transistors having channels coupled in series between said inverted clock signal and said negative power supply level, said inverted clock signal being applied to a gate of said eleventh transistor, a gate of said twelfth transistor being coupled to a junction point between the channels of said ninth and tenth transistors, and a junction point between the channels of said eleventh and twelfth transistors being coupled to said gate of said eighth transistor.

Claim 7

The clock generator circuit of claim 5, wherein said means for inverting said input clock signal comprises thirteenth and fourteenth transistors having channels coupled in series between said positive power supply level and ground, a gate of said thirteenth transistor being coupled to said positive power supply level, said input clock signal being applied to a gate of said fourteenth transistor, said inverted clock signal being produced at a junction point between the channels of said thirteenth and fourteenth transistors.

Claim 8

A clock generator circuit for producing an output clock signal having levels determined by positive and negative power supply levels in response to an input clock signal having levels determined by said postive power supply level and a ground level, comprising: a first FET having a drain and gate coupled to said positive power supply level; a second FET having a drain connected to a source of said of first FET and a gate coupled to said positive power supply level; a third FET having a source coupled to ground and a drain coupled to a source of said second FET, said input clock signal being applied to a gate of said third FET; a fourth FET having a drain and gate coupled to said drain of said third FET; a fifth FET having a drain coupled to a source of said fourth FET and a source coupled to ground, said input clock signal being applied to a gate of said fifth FET; a sixth FET having a source coupled to said negative power supply level and a drain coupled to said source of said fourth FET and said drain of said fifth FET, a channel resistance of said sixth FET when turned on being less than a channel resistance of said fifth FET when turned on; a seventh FET, said input clock signal being applied to a drain and gate of said seventh FET, a source of said seventh FET being coupled to a gate of said sixth FET; an eighth FET having a drain coupled to said source of said seventh FET and a source coupled to said negative power supply level; a ninth FET having a drain coupled to said positive power supply level and a gate coupled to said source of said seventh FET; a capacitor coupled between a source of said ninth FET and said source of said seventh FET; a tenth FET having a drain coupled to said source of said ninth FET, a gate coupled to said drain of said sixth FET, and a source coupled to said negative power supply level; an eleventh FET having a drain coupled to said positive power supply level and a gate coupled to said gate of said ninth FET; a twelfth FET having a drain coupled to a source of said eleventh FET, a gate coupled to said gate of said tenth FET, and a source coupled to said negative power supply level, said output clock signal being produced at said drain of said twelfth FET; a thirteenth FET, said input clock signal being applied to a drain and gate of said thirteenth FET; a fourteenth FET having a drain coupled to a source of said thirteenth FET, a gate coupled to said drain of said third FET, and a source coupled to said negative power supply level; a fifteenth FET having a drain and gate coupled to said drain of said third FET; and a sixteenth FET having a drain coupled to a source of said fifteenth FET and a gate of said eighth FET, a gate coupled to said drain of said fourteenth FET, and a source coupled to said negative power supply level.

Claim 9

A clock generator circuit for producing an output clock signal having levels determined by positive and negative power supply levels in response to an input clock signal having levels determined by said postive power supply level and a ground level, comprising: a first FET having a drain and gate coupled to said positive power supply level; a second FET having a drain connected to a source of said of first FET and a gate coupled to said positive power supply level; a third FET having a source coupled to ground and a drain coupled to a source of said second FET, said input clock signal being applied to a gate of said third FET; a fourth FET having a drain and gate coupled to said drain of said third FET; a fifth FET having a drain coupled to a source of said fourth FET and a source coupled to ground, said input clock signal being applied to a gate of said fifth FET; a sixth FET having a source coupled to said negative power supply level and a drain coupled to said source of said fourth FET and said drain of said fifth FET, a channel resistance of said sixth FET when turned on being less than a channel resistance of said fifth FET when turned on; a seventh FET, said input clock signal being applied to a drain and gate of said seventh FET, a source of said seventh FET being coupled to a gate of said sixth FET; an eighth FET having a drain coupled to said source of said seventh FET and a source coupled to said negative power supply level; a ninth FET having a drain coupled to said positive power supply level and a gate coupled to said source of said seventh FET; a capacitor coupled between a source of said ninth FET and said source of said seventh FET; a tenth FET having a drain coupled to said source of said ninth FET, a gate coupled to said drain of said sixth FET, and a source coupled to said negative power supply level; an eleventh FET having a drain coupled to said positive power supply level and a gate coupled to said gate of said ninth FET; a twelfth FET having a drain coupled to a source of said eleventh FET, a gate coupled to said gate of said tenth FET, and a source coupled to said negative power supply level, said output clock signal being produced at said drain of said twelfth FET; a thirteenth FET, said input clock signal being applied to a drain and gate of said thirteenth FET; a fourteenth FET having a drain coupled to a source of said thirteenth FET, a gate coupled to said drain of said third FET, and a source coupled to said negative power supply level; a fifteenth FET having a drain and gate coupled to said drain of said third FET; and a sixteenth FET having a drain coupled to a source of said fifteenth FET and a gate of said eighth FET, a gate coupled to said drain of said fourteenth FET, and a source coupled to said negative power supply level.

Claim 12

The method for producing an output clock signal of claim 8, wherein said step of connecting said control electrode of said first transistor to said negative power supply level comprises turning on a fourth transistor in response to said charge on said bootstrap capacitor reaching said predetermined level to connect said control electrode of said first transistor to said negative power level through a channel of said fourth transistor.

Claim 13

The method for producing an output clock signal of claim 9, further comprising the step of, when said input clock signal makes a transition from said high state to said low state, discharging said bootstrap capacitor.