Stable fast-settling voltage reference buffer amplifier

Claim 2

A stable fast-settling buffer configuration comprising an amplifier having input and output terminals, first and second stages decoupled from each other and responsive to a voltage appearing at said output terminal for providing identical output voltages at first and second node points, respectively, said second node point being adapted to be connected to a load, and a feedback path connected between said first node point and the input terminal of said amplifier, wherein said amplifier includes an additional input terminal and wherein a reference voltage source is connected to said additional input terminal, wherein a capacitive load is connected to said second node point, wherein said first and second stages comprise first and second source follower circuits, respectively, wherein each of said first and second source follower circuits comprises a current source in series with the source-to-drain path of an MOS transistor, wherein the output terminal of said amplifier is directly connected to the gate of the transistor in said first source follower circuit and is connected to the gate of the transistor in said second source follower circuit via a decoupling element, and wherein the current source in said second source follower circuit supplies a current that is N times that supplied by the current source in said first source follower circuit, where N is a positive number, and wherein the β of the transistor in said second source follower circuit is N times that of the transistor in said first source follower circuit.

Claim 3

A buffer amplifier adapted to be interposed between a reference voltage source and a capacitive load, said buffer amplifier comprising a two-input-terminal operational amplifier having an output terminal, one input terminal being adapted to be connected to the output of a reference voltage source and the other input terminal being adapted to be connected to a feedback path, first and second scaled source follower circuits respectively including MOS transistors whose gate-to-source voltages are designed to be the same, means for applying the voltage appearing at the output terminal of said operational amplifier to the gates of said transistors, said means including a decoupling element connected between said output terminal and the gate of the transistor in said second circuit, and a feedback path connected between the source of the transistor in said first circuit and the other input terminal of said operational amplifier, whereby perturbations or phase shifts arising from a capacitive load connected to the source of the transistor in said second circuit are effectively decoupled from said operational amplifier thereby to provide a relatively stable and fast-settling buffer amplifier, wherein each of said source follower circuits includes a constant current source connected to the source of the transistor included in said circuit, and wherein the constant current source in said second circuit is adapted to supply a current N times that supplied by the constant current source in said first circuit, and wherein the β of the transistor in said second circuit is designed to be N times that of the transistor in said first circuit.

Claim 4

A buffer amplifier adapted to be interposed between a reference voltage source and a capacitive load, said buffer amplifier comprising a two-input-terminal operational amplifier having an output terminal, one input terminal being adapted to be connected to the output of a reference voltage source and the other input terminal being adapted to be connected to a feedback path, first and second scaled source follower circuits respectively including MOS transistors whose gate-to-source voltages are designed to be the same, means for applying the voltage appearing at the output terminal of said operational amplifier to the gates of said transistors, said means including a decoupling element connected between said output terminal and the gate of the transistor in said second circuit, and a feedback path connected between the source of the transistor in said first circuit and the other input terminal of said operational amplifier, whereby perturbations or phase shifts arising from a capacitive load connected to the source of the transistor in said second circuit are effectively decoupled from said operational amplifier thereby to provide a relatively stable and fast-settling buffer amplifier, wherein each of said source follower circuits includes a constant current source connected to the source of the transistor included in said circuit, and wherein the constant current source in said second circuit is adapted to supply a current N times that supplied by the constant current source in said first circuit, and wherein the β of the transistor in said second circuit is designed to be N times that of the transistor in said first circuit.

Claim 5

An amplifier as in claim 2 wherein said feedback path includes an adjustable resistive network for controlling the value of the voltage available at the output terminal of said operational amplifier and thereby also the value of the voltage available at the source of the transistor in said second circuit.

Claim 6

An amplifier as in claim 3 further including a decoupling capacitor connected to the source of the transistor in said second circuit.

Claim 7

A stable fast-settling buffer configuration comprising an amplifier having input and output terminals, first and second stages decoupled from each other and responsive to a voltage appearing at said output terminal for providing identical output voltages at first and second node points, respectively, said second node point being adapted to be connected to a load, and a feedback path connected between said first node point and the input terminal of said amplifier, wherein said amplifier includes an additional input terminal to which a reference voltage source is adapted to be connected, wherein said first and second stages comprise first and second source follower circuits, respectively, wherein each of said first and second source follower circuits comprises a current source in series with the source-to-drain path of an MOS transistor, wherein the output terminal of said amplifier is directly connected to the gate of the transistor in said first source follower circuit and is connected to the gate of the transistor in said second source follower circuit via a decoupling element, and wherein the current source in said second source follower circuit supplies a current that is N times that supplied by the current source in said first source follower circuit, where N is a positive number, and wherein the β of the transistor in said second source follower circuit is N times that of the transisitor in said first source follower circuit.

Claim 8

A stable fast-settling buffer configuration comprising an amplifier having input and output terminals, first and second stages decoupled from each other and responsive to a voltage appearing at said output terminal for providing identical output voltages at first and second node points, respectively, said second node point being adapted to be connected to a load, and a feedback path connected between said first node point and the input terminal of said amplifier, wherein said amplifier includes an additional input terminal to which a reference voltage source is adapted to be connected, wherein said first and second stages comprise first and second source follower circuits, respectively, wherein each of said first and second source follower circuits comprises a current source in series with the source-to-drain path of an MOS transistor, wherein the output terminal of said amplifier is directly connected to the gate of the transistor in said first source follower circuit and is connected to the gate of the transistor in said second source follower circuit via a decoupling element, and wherein the current source in said second source follower circuit supplies a current that is N times that supplied by the current source in said first source follower circuit, where N is a positive number, and wherein the β of the transistor in said second source follower circuit is N times that of the transisitor in said first source follower circuit.