Microcomputer having data shift within memory

Claim 2

A microcomputer device formed in a single integrated circuit comprising: an arithmetic/logic unit having a data input and a data output; a data memory having an array of memory locations for storing data words; said data memory having data input/output means, and having addressing means for accessing locations of data words in the array for store and recall of data words via said input/output means; data bus means coupled to the data input and data output of the arithmetic/logic unit and to the data input/output means of the data memory; shift means included in said data memory means, said shift means moving an entire data word in the memory from one location in the array to another location having an adjacent address, said data word being shifted within said shift means through a shift path that does not include said data bus means and without being coupled through said arithmetic/logic means to implement the shift.

Claim 3

A device according to claim 1 wherein a data word being recalled from said data memory is applied to the data bus means and to the input of the arithmetic/logic unit from the data input/output means of the data memory during one part of an operating cycle, and a data word being stored in said data memory is applied from the data bus via the data input/output means to a location in the data memory during a subsequent part of said operating cycle.

Claim 4

A device according to claim 2 wherein the shift means operates during a period between said one part and said subsequent part of an operating cycle.

Claim 5

A device according to claim 3 wherein the addressing means of the data memory changes from addressing said one location to addressing said another location, and said change occurs during said period.

Claim 6

A device according to claim 4 said shift means includes means for temporarily holding a data word recalled from said one location at said data input/output means for a time interval from said one part to said subsequent part of an operating cycle.

Claim 7

A device according to claim 4 wherein the data memory includes an array of rows and columns of read/write memory cells and each row accesses a data word, the adjacent location being an adjacent row.

Claim 8

A device according to claim 1 including control means having an input and means for loading instruction words to said input; said control means having outputs coupled to said arithmetic/logic unit, to said data memory, to said data bus means, and to said shift means; said shift means in response to said outputs of said control means produced by one of said instruction words functioning to recall said data word from said one location and to store said data word in said another location.

Claim 9

A microcomputer system comprising: (a) a microcomputer device formed in a single integrated circuit and having data input/output terminals and address output terminals; (b) memory means external to the microcomputer device having an address input and data output means; (c) input/output means separate from said microcomputer device and from said memory means for transfer of information from the microcomputer device to external equipment, or for transfer of information from external equipment to the microcomputer device; the input/output means having an address input and data input/output terminals; (d) external address bus means coupled to the address output terminals of the microcomputer device and to the address input of the memory means and of the input/output means; (e) external data bus means coupled to the data input/output terminals of the microcomputer device coupled to the data output means of the memory means, and coupled to the data input/output terminals of the input/output means; (f) the microcomputer device comprising: an arithmetic/logic unit having data input and data output, and having control inputs; an internal data memory having an address input and having data input/output means; program accessing means having a program counter and an address output and having an instruction register, the program accessing means fetching instruction words and storing the instruction words one-at-a-time in said instruction register; and means connecting said address output to said address output terminals; control means having input means to receive an instruction word, said control means generating controls at control outputs in response to said instruction word, controls from said control outputs being coupled to said control inputs of the arithemtic/logic unit for defining operation of the arithmetic/logic unit; internal data bus means coupled to the data input and data output of the arithmetic/logic unit and coupled to the data input/output means of the internal data memory, the internal data bus means including control elements receiving controls from said control outputs of the control means; internal program bus means coupled to said instruction register and coupled to said input means of said control means, the internal program bus means also including control elements receiving controls from said control outputs of the control means; clocking means having outputs coupled to said arithmetic/logic unit, said internal data and program bus means, and said control means, to define repetitive machine cycles; said internal data memory including an array of rows and columns of read/write memory cells, and having addressing means selecting one of a plurality of locations of data words defined by a row and column address applied to said address input; the data word selected by a row and column address being coupled to said data input/output means for a read operation; and data shift means in said internal data memory operative in response to said control outputs to move a data word from a location selected by said row and column address to an adjacent location in said internal data memory within one of said machine cycles by a path which does not include said internal data bus means or said arithmetic/logic unit.

Claim 10

A microcomputer system comprising: (a) a microcomputer device formed in a single integrated circuit and having data input/output terminals and address output terminals; (b) memory means external to the microcomputer device having an address input and data output means; (c) input/output means separate from said microcomputer device and from said memory means for transfer of information from the microcomputer device to external equipment, or for transfer of information from external equipment to the microcomputer device; the input/output means having an address input and data input/output terminals; (d) external address bus means coupled to the address output terminals of the microcomputer device and to the address input of the memory means and of the input/output means; (e) external data bus means coupled to the data input/output terminals of the microcomputer device coupled to the data output means of the memory means, and coupled to the data input/output terminals of the input/output means; (f) the microcomputer device comprising: an arithmetic/logic unit having data input and data output, and having control inputs; an internal data memory having an address input and having data input/output means; program accessing means having a program counter and an address output and having an instruction register, the program accessing means fetching instruction words and storing the instruction words one-at-a-time in said instruction register; and means connecting said address output to said address output terminals; control means having input means to receive an instruction word, said control means generating controls at control outputs in response to said instruction word, controls from said control outputs being coupled to said control inputs of the arithemtic/logic unit for defining operation of the arithmetic/logic unit; internal data bus means coupled to the data input and data output of the arithmetic/logic unit and coupled to the data input/output means of the internal data memory, the internal data bus means including control elements receiving controls from said control outputs of the control means; internal program bus means coupled to said instruction register and coupled to said input means of said control means, the internal program bus means also including control elements receiving controls from said control outputs of the control means; clocking means having outputs coupled to said arithmetic/logic unit, said internal data and program bus means, and said control means, to define repetitive machine cycles; said internal data memory including an array of rows and columns of read/write memory cells, and having addressing means selecting one of a plurality of locations of data words defined by a row and column address applied to said address input; the data word selected by a row and column address being coupled to said data input/output means for a read operation; and data shift means in said internal data memory operative in response to said control outputs to move a data word from a location selected by said row and column address to an adjacent location in said internal data memory within one of said machine cycles by a path which does not include said internal data bus means or said arithmetic/logic unit.

Claim 11

A microcomputer system according to claim 8 wherein said data shift means and said addressing means and data input/output means all operate in response to control outputs generated from a single one of said instruction words.