Hexadecimal digit shifter output control by a programmable read only memory

Claim 2

A shifter unit for performing scientific arithmetic operations comprising: shifting means for receiving a mantissa and responsive to a plurality of shift signals for generating a plurality of shifter signals indicative of said mantissa shifted a number of positions specified by said shift signals; multiplexer means coupled to said shifting means for receiving said shifter signals for transfer to an output; read only memory means responsive to said plurality of shift signals for generating a plurality of enabling signals in a first state and a plurality of enabling signals in a second state, said multiplexer means being coupled to said read only memory means and responsive to said enabling signals in said first state for transferring said plurality of shifter signals, and responsive to said enabling signals in said second state for transferring characters having a value of ZERO to said output.

Claim 3

The shifter unit of claim 1 wherein said unit further comprises: control means coupled to said multiplexer means and said read only memory means for generating a first plurality of control signals for defining a type of operation and a second plurality of control signals for defining constants and masks.

Claim 4

The shifter unit of claim 2 wherein said multiplexer means comprises: a plurality of multiplexer circuits having said plurality of shifter signals applied to a first terminal, and register signals and said second plurality of control signals applied to a second terminal of selected ones of said plurality of multiplexer circuits, said multiplexer circuits being responsive to a first control signal in a first state or a second control signal in a second state of said first plurality of control signals for selecting said first terminal for transferring said plurality of shifter signals and said first control signal in said second state and said second control signal in said first state for selecting said second terminal for transferring said register signals and said second plurality of control signals to said output.

Claim 5

The shifter unit of claim 3 wherein each of said plurality of multiplexer circuits is responsive to an enabling signal of said plurality of enabling signals in said first state for transferring a hexadecimal character indicated by said plurality of shifter signals, said register signals, or said second plurality of control signals to said output, and said enabling signal in said second state for transferring one of said characters having said value of ZERO to said output.

Claim 6

The shifter unit of claim 4 wherein said read only memory means comprises: a programmable read only memory having a plurality of address locations, each address location having a plurality of bit positions, each bit position storing a binary ONE or a binary ZERO, said programmable read only memory generating one of said plurality of enabling signals for each of said plurality of bit positions, said enabling signal in said first state being generated by said bit position storing said binary ZERO and said enabling signal in said second state being generated by said bit position storing said binary ONE, said one of said plurality of enabling signals being applied to each of said plurality of multiplexer circuits respectively.

Claim 7

The shifter unit of claim 5 wherein said read only memory means is responsive to said shift signals and to said first control signal in a second state and said second control signal in said second state for generating said enabling signals in said first state for enabling each of said plurality of multiplexer circuits for effecting an end around shift.

Claim 8

The shifter unit of claim 6 wherein said read only memory means is responsive to said shift signals and to said first control signal in said first state and said second control signal in said second state for generating said enabling signals in said first state for enabling a first set of said multiplexers for transferring said shifter signals mantissas to said output and for generating said enabling signals in said second state for disabling a second set of said multiplexers for transferring said ZERO characters to said output, said ZERO characters being in the high order positions of an operand including said mantissa and said ZERO characters; said read only memory means generating said enabling signal in said second state for said each of said multiplexer circuits for transferring said operand having said ZERO characters in all of said operand character positions when said shift signals indicate a shift of greater than the number of said operand character positions.

Claim 9

The shifter unit of claim 7 wherein said read only memory means is responsive to said shift signals, said first control signal in said second state, and said second control signal in said first state for generating said enabling signals in said first state for enabling said selected ones of said plurality of multiplexer circuits, said first control signal in said second state and said second control signal in said first state selecting said second terminals of said multiplexers for transfer of selected ones of said register signals or said second plurality of control signals to said output.

Claim 10

The shifter unit of claim 8 wherein said read only memory means is responsive to said shift signals and said first and said second control signals in said second state for generating said enabling signals in said second state for disabling said multiplexer circuits that suppress the number of character positions equal to a register size of said output, and generating said enabling signals in said first state for enabling said multiplexer circuits for transferring precision error characters to said output, said operand having a number of ZERO characters equal to said register size in the left character positions of said operand and said precision error characters in the right character positions of said operand, said operand indicating a precision error if at least one of said precision error characters is not a ZERO character.

Claim 11

The shifter unit of claim 9 wherein said characters are hexadecimal characters.

Claim 12

A processor for performing scientific arithmetic comprising: random access memory means for storing a first operand comprising a first exponent and a first mantissa, and a second operand comprising a second exponent and a second mantissa; first arithmetic logic unit means coupled to said random access means for generating shift signals indicative of the difference between said first and said second exponents; address selection means coupled to said first arithmetic logic means and said random access memory means for selecting said first mantissa if said first exponent is smaller than said second exponent and selecting said second mantissa if said second exponent is smaller than said first exponent; shifting means coupled to said random access memory means and to said first arithmetic logic means for receiving said selected mantissa for shifting a number of positions indicated by said shift signals; second arithmetic logic means coupled to said random access memory means and to said shifting means for receiving said selected mantissa, shifted said number of positions; wherein said shifting means include: shifter means for receiving said selected mantissa and responsive to said shift signals for generating a plurality of shifter signals indicative of said selected mantissa shifted said number of positions; multiplexer means coupled to said shifter means for receiving said shifter signals for transfer to said second arithmetic logic means; read only memory means responsive to said plurality of shift signals for generating a plurality of enabling signals in a first state and a plurality of enabling signal, in a second state, said multiplexer means being coupled to said read only memory means and responsive to said enabling signals in said first state for transferring said plurality of shifter signals, and responsive to said enabling signals in said second state for transferring characters having a value of ZERO to said second arithmetic logic means.

Claim 13

A processor for performing scientific arithmetic comprising: random access memory means for storing a first operand comprising a first exponent and a first mantissa, and a second operand comprising a second exponent and a second mantissa; first arithmetic logic unit means coupled to said random access means for generating shift signals indicative of the difference between said first and said second exponents; address selection means coupled to said first arithmetic logic means and said random access memory means for selecting said first mantissa if said first exponent is smaller than said second exponent and selecting said second mantissa if said second exponent is smaller than said first exponent; shifting means coupled to said random access memory means and to said first arithmetic logic means for receiving said selected mantissa for shifting a number of positions indicated by said shift signals; second arithmetic logic means coupled to said random access memory means and to said shifting means for receiving said selected mantissa, shifted said number of positions; wherein said shifting means include: shifter means for receiving said selected mantissa and responsive to said shift signals for generating a plurality of shifter signals indicative of said selected mantissa shifted said number of positions; multiplexer means coupled to said shifter means for receiving said shifter signals for transfer to said second arithmetic logic means; read only memory means responsive to said plurality of shift signals for generating a plurality of enabling signals in a first state and a plurality of enabling signal, in a second state, said multiplexer means being coupled to said read only memory means and responsive to said enabling signals in said first state for transferring said plurality of shifter signals, and responsive to said enabling signals in said second state for transferring characters having a value of ZERO to said second arithmetic logic means.

Claim 14

The shifter unit of claim 11 wherein said unit further comprises: control means coupled to said multiplexer means and said read only memory means for generating a first plurality of control signals for defining a type of operation and a second plurality of control signals for defining constants and masks.

Claim 15

The shifter of claim 12 wherein said multiplexer means comprises: a plurality of multiplexer circuits having said plurality of shifter signals applied to a first terminal, and register signals and said second plurality of control signals applied to a second terminal of selected ones of said plurality of multiplexer circuits, said multiplexer circuits being responsive to a first control signal in a first state or a second control signal in a second state of said first plurality of control signals for selecting said first terminal for transferring said plurality of shifter signals and said first control signal in said second state and said second control signal in said first state for selecting said second terminal for transferring said register signals and said second plurality of control signals to said second arithmetic logic means.

Claim 16

The shifter unit of claim 13 wherein each of said plurality of multiplexer circuits is responsive to an enabling signal of said plurality of enabling signals in said first state for transferring a character indicated by said plurality of shifter signals, said register signals, or said second plurality of control signals to said second arithmetic logic unit output, and said enabling signal in said second state for transferring one of said characters having said value of ZERO to said output.

Claim 17

The shifter unit of claim 14 wherein said read only memory means comprises: a programmable read only memory having a plurality of address locations, each address location having a plurality of bit positions, each bit position storing a binary ONE or a binary ZERO, said programmable read only memory generating one of said plurality of enabling signals for each of said plurality of bit positions, said enabling signal in said first state being generated by said bit position storing said binary ZERO and said enabling signal in said second state being generated by said bit position storing said binary ONE, said one of said plurality of enabling signals being applied to each of said plurality of multiplexer circuits respectively.

Claim 18

The shifter unit of claim 15 wherein said read only memory means is responsive to said shift signals and to said first control signal in a second state and said second control signal in said second state for generating said enabling signals in said first state for enabling each of said plurality of multiplexer circuits for effecting an end around shift.

Claim 19

The shifter unit of claim 16 wherein said read only memory means is responsive to said shift signals and to said first control signal in said first state and said second control signal in said second state for generating said enabling signals in said first state for enabling a first set of said multiplexers for transferring said shifter signals to said second arithmetic logic means and for generating said enabling signals in said second state for disabling a second set of said multiplexers for transferring said ZERO characters to said second arithmetic logic means, said ZERO characters being in the high order positions of an operand including said mantissa and said ZERO characters; said read only memory means generating said enabling signal in said second state for said each of said multiplexer circuits for transferring said operand having said ZERO characters in all of said operand character positions when said shift signals indicate a shift of greater than the number of said operand character positions.

Claim 20

The shifter unit of claim 17 wherein said read only memory means is responsive to said shift signals, said first control signal in said second state, and said second control signal in said first state for generating said enabling signals in said first state for enabling said selected ones of said plurality of multiplexer circuits, said first control signal in said second state and said second control signal in said first state selecting said second terminal of said multiplexers for transfer of selected ones of said register signals or said second plurality of control signals to said second arithmetic logic means.

Claim 21

The shifter unit of claim 18 wherein said read only memory means is responsive to said shift signals and said first and said second control signals in said second state for generating said enabling signals in said second state for disabling said multiplexer circuits that suppress the number of character positions equal to a register size of a central processor register, and generating said enabling signals in said first state for enabling said multiplexer circuits for transferring precision error characters to said second arithmetic logic means, said operand having a number of ZERO characters equal to said register size in the left character positions of said operand and said precision error characters in the right character positions of said operand, said operand indicating a precision error if at least one of said precision error characters is not a ZERO character.

Claim 22

The shifter unit of claim 19 wherein said characters are hexadecimal characters.