Floating point arithmetic unit adapted for converting a computer to floating point arithmetic

Claim 2

A floating point system adapted for coupling to a computer for providing a plurality of floating point arithmetic operations, said system comprising: first exponent and mantissa input means, second exponent and mantissa input means, an output shift register means for storing and providing the mantissa output of said system, a parallel adder coupled for receiving an output of said output shift register means and for receiving a first input mantissa from said first mantissa input means and for supplying the sum of the two, a quotient register for receiving and storing a most significant bit of the output of said adder, and gating means forming a loop circuit with said adder and said output shift register for selectively gating the output of said adder, the output of said quotient register, and the output of said second mantissa input means into said output shift register means.

Claim 3

The system according to claim 1 further including means under the control of the sign of respective inputs and the function to be carried out for selectively complementing the output of said mantissa input means as applied respectively to said adder and said gating means, and for further selectively complementing the output of said output shift register means as applied to said adder.

Claim 4

The system according to claim 1 further including input coupling means for providing an integer input to said gating means for alternative coupling to said output shift register means.

Claim 5

The system according to claim 1 further including adding means for receiving the first and second exponents from the first and second exponent input means and for selectively adding, subtracting and selecting the larger of said exponents, and counter register means for receiving a selected output of said adding means to provide a floating point exponent output.

Claim 6

The system according to claim 4 further including means for incrementing and decrementing said counter register means while respectively right-shifting or left-shifting the contents of said output shift register means.

Claim 7

A floating point system for selectively performing a plurality of arithmetic operations, said system comprising: an exponent circuit comprising means for selectively adding, subtracting and selecting the larger of a pair of input exponents, and a mantissa circuit comprising a first digital register, a second digital register, and a computing loop including a shift register, adding means, and gating means wherein Said shift register is coupled to supply mantissa information to said adding means for addition to a mantissa input value from a first digital register, and said gating means is connected for coupling the sum output of said adding means into said shift register in a cycle of operation, said gating means being alternatively operable for suppling other mantissa information to said loop comprising information from said second digital register, and means for shifting information in said shift register for application of the shift register''s output to said adding means in selected arithmetic operations.

Claim 8

A floating point system for selectively performing a plurality of arithmetic operations, said system comprising: an exponent circuit comprising means for selectively adding, subtracting and selecting the larger of a pair of input exponents, and a mantissa circuit comprising a first digital register, a second digital register, and a computing loop including a shift register, adding means, and gating means wherein Said shift register is coupled to supply mantissa information to said adding means for addition to a mantissa input value from a first digital register, and said gating means is connected for coupling the sum output of said adding means into said shift register in a cycle of operation, said gating means being alternatively operable for suppling other mantissa information to said loop comprising information from said second digital register, and means for shifting information in said shift register for application of the shift register''s output to said adding means in selected arithmetic operations.

Claim 9

A floating point system for providing a plurality of arithmetic operations and adapted for coupling to a computer comprising: a first digital register, a second digital register, and a shift register, each of said registers having substantially similar capacity in number of stages for each storing the digits of floating point mantissa words, an adder comprising means for selectively performing addition on mantissa digits derived from said registers, a loop circuit including said shift register and said adder wherein said adder is coupled to receive a mantissa input from the first digital register for adding the same to the output of said shift register as received in said loop circuit, while providing a sum output in said loop circuit for entry back into said shift register in a single cycle for replacing prior information located therewithin, and including gating means coupled with said loop circuit for selectively coupling the sum output of said adder into said shift register and for selectively coupling mantissa information from the second digital register into said shift register with the same relative placement in said shift register as the sum output of said adder for arithmetic operation thereupon in said loop circuit including said adder.

Claim 10

A floating point system for providing a plurality of arithmetic operations and adapted for coupling to a computer comprising: a first digital register, a second digital register, and a shift register, each of said registers having substantially similar capacity in number of stages for each storing the digits of floating point mantissa words, an adder comprising means for selectively performing addition on mantissa digits derived from said registers, a loop circuit including said shift register and said adder wherein said adder is coupled to receive a mantissa input from the first digital register for adding the same to the output of said shift register as received in said loop circuit, while providing a sum output in said loop circuit for entry back into said shift register in a single cycle for replacing prior information located therewithin, and including gating means coupled with said loop circuit for selectively coupling the sum output of said adder into said shift register and for selectively coupling mantissa information from the second digital register into said shift register with the same relative placement in said shift register as the sum output of said adder for arithmetic operation thereupon in said loop circuit including said adder.

Claim 11

A floating point system for providing a plurality of arithmetic operations and adapted for coupling to a computer comprising: a loop circuit including a shift register and an adder wherein said shift register is coupled to receive one input, and said adder is coupled to receive another input for adding the same to the output of said shift register as received in said loop circuit, while providing an output in said loop circuit for entry back into said shift register in a single cycle for replacing prior information located therewithin, said loop circuit including gating means for selectively coupling the output of said adder to said shift register, and coupling information external to said loop circuit into said shift register, and including quotient register means adapted to receive successive bits produced by successive additions by said adder and for alternatively providing a quotient output to said shift register via said gating means.

Claim 12

A floating point system for providing a plurality of arithmetic operations and adapted for coupling to a computer comprising: a loop circuit including a shift register and an adder wherein said shift register is coupled to receive one input, and said adder is coupled to receive another input for adding the same to the output of said shift register as received in said loop circuit, while providing an output in said loop circuit for entry back into said shift register in a single cycle for replacing prior information located therewithin, said loop circuit including gating means for selectively coupling the output of said adder to said shift register, and coupling information external to said loop circuit into said shift register, and including quotient register means adapted to receive successive bits produced by successive additions by said adder and for alternatively providing a quotient output to said shift register via said gating means.

Claim 13

A floating point system for selectively performing a plurality of arithmetic operations, said system comprising: an exponent circuit comprising means for selectively adding, subtracting and selecting the larger of a pair of input exponents, and a mantissa circuit comprising a computing loop including a register, adding means, and gating means therebetween wherein said register is coupled to supply information to said adding means for addition to an input value, and said gating means is connected for coupling the output of said adding means into said register in a cycle of operation, said gating means being alternatively operable for supplying external information to said register means, and including means for selectively complementing the output of said register as applied to said adding means, and means for shifting information in said register for application of the register''s output to said adding means in selected arithmetic operations.

Claim 14

A floating point system for selectively performing a plurality of arithmetic operations, said system comprising: an exponent circuit comprising means for selectively adding, subtracting and selecting the larger of a pair of input exponents, and a mantissa circuit comprising a computing loop including a register, adding means, and gating means therebetween wherein said register is coupled to supply information to said adding means for addition to an input value, and said gating means is connected for coupling the output of said adding means into said register in a cycle of operation, said gating means being alternatively operable for supplying external information to said register means, and including means for selectively complementing the output of said register as applied to said adding means, and means for shifting information in said register for application of the register''s output to said adding means in selected arithmetic operations.

Claim 15

A floating point system for selectively performing a plurality of arithmetic operations, said system comprising: an exponent circuit comprising means for selectively addIng, subtracting and selecting the larger of a pair of input exponents, and a mantissa circuit comprising a computing loop including a first register, adding means, and gating means therebetween wherein said first register is coupled to supply information to said adding means for addition to an input value, and said gating means is connected for coupling the output of said adding means into said first register in a cycle of operation, said gating means being alternatively operable for supplying external information to said first register, means for shifting information in said first register for application of the register''s output to said adding means in selected arithmetic operations, a quotient register for selectively receiving output bits from said adding means upon successive subtractions provided by said adding means and means for coupling the output of said quotient register via said gating means as an input to said first register, and means for selectively operating said gating means in accordance with the state of successive of said output bits from said adding means for replacing the information in said first register with the result of said subtraction.

Claim 16

A floating point system for selectively performing a plurality of arithmetic operations, said system comprising: an exponent circuit comprising means for selectively addIng, subtracting and selecting the larger of a pair of input exponents, and a mantissa circuit comprising a computing loop including a first register, adding means, and gating means therebetween wherein said first register is coupled to supply information to said adding means for addition to an input value, and said gating means is connected for coupling the output of said adding means into said first register in a cycle of operation, said gating means being alternatively operable for supplying external information to said first register, means for shifting information in said first register for application of the register''s output to said adding means in selected arithmetic operations, a quotient register for selectively receiving output bits from said adding means upon successive subtractions provided by said adding means and means for coupling the output of said quotient register via said gating means as an input to said first register, and means for selectively operating said gating means in accordance with the state of successive of said output bits from said adding means for replacing the information in said first register with the result of said subtraction.

Claim 17

A floating point system for providing a plurality of arithmetic operations and adapted for coupling to a computer comprising: at least three digital registers wherein at least one such register comprises a shift register, each such register having substantially similar capacity in number of stages for each storing the digits of floating point mantissa words, an adder comprising means for selectively performing addition on mantissa digits derived from said registers, a loop circuit including said shift register and said adder wherein said adder is coupled to receive a mantissa input from one of the remaining registers for adding the same to the output of said shift register while providing an adder output in said loop circuit for substantially immediate entry back into said shift register, and means for entering mantissa information from another of said remaining registers into said loop circuit with the same relative digital placement in said loop circuit as other information circulated in said loop circuit for arithmetic operation thereupon in said loop circuit including said adder.

Claim 18

A floating point system for providing a plurality of arithmetic operations and adapted for coupling to a computer comprising: at least three digital registers wherein at least one such register comprises a shift register, each such register having substantially similar capacity in number of stages for each storing the digits of floating point mantissa words, an adder comprising means for selectively performing addition on mantissa digits derived from said registers, a loop circuit including said shift register and said adder wherein said adder is coupled to receive a mantissa input from one of the remaining registers for adding the same to the output of said shift register while providing an adder output in said loop circuit for substantially immediate entry back into said shift register, and means for entering mantissa information from another of said remaining registers into said loop circuit with the same relative digital placement in said loop circuit as other information circulated in said loop circuit for arithmetic operation thereupon in said loop circuit including said adder.

Claim 19

A floating point system for providing a plurality of arithmetic operations and adapted for coupling to a computer comprising: at least three digital registers wherein at least one such register comprises a shift register, an adder, a loop circuit including said shift register and said adder wherein said adder is coupled to receive a mantissa input from one of the remaining registers for adding the same to the output of said shift register while providing an adder output in said loop circuit for substantially immediate entry back into said shift register, and means for successively shifting information in said shift register while controlling successive addition operations in said adder in response to the presence of successive digits of a multiplier in another remaining register.

Claim 20

A floating point system for providing a plurality of arithmetic operations and adapted for coupling to a computer comprising: at least three digital registers wherein at least one such register comprises a shift register, an adder, a loop circuit including said shift register and said adder wherein said adder is coupled to receive a mantissa input from one of the remaining registers for adding the same to the output of said shift register while providing an adder output in said loop circuit for substantially immediate entry back into said shift register, and means for successively shifting information in said shift register while controlling successive addition operations in said adder in response to the presence of successive digits of a multiplier in another remaining register.

Claim 21

A floating point system for providing a plurality of arithmetic operations and adapted for coupling to a computer comprising: a loop circuit including a shift register and an adder wherein said shift register receives one input and said adder receives another input for adding the same to the output of said shift register, providing an algebraic sum in said loop circuit for selective entry back into said shift register for selectively replacing prior information located therewithin, means coupled to the loop circuit for selectively coupling the sum output of said adder back into said loop circuit for entry into the shift register and for coupling other information external to said loop circuit into said loop circuit, and including quotient register means coupled to said adder and responsive to successive additions by said adder for alternatively providing a quotieNt output.

Claim 22

A floating point system for providing a plurality of arithmetic operations and adapted for coupling to a computer comprising: a loop circuit including a shift register and an adder wherein said shift register receives one input and said adder receives another input for adding the same to the output of said shift register, providing an algebraic sum in said loop circuit for selective entry back into said shift register for selectively replacing prior information located therewithin, means coupled to the loop circuit for selectively coupling the sum output of said adder back into said loop circuit for entry into the shift register and for coupling other information external to said loop circuit into said loop circuit, and including quotient register means coupled to said adder and responsive to successive additions by said adder for alternatively providing a quotieNt output.

Claim 23

A floating point system for providing a plurality of arithmetic operations and adapted for coupling to a computer comprising: a first digital register, a second digital register, a loop circuit including a shift register and an adder wherein said adder is coupled to receive a mantissa input from the first digital register for adding the same to the output of said shift register as received in said loop circuit, while providing a sum output in said loop circuit for entry back into said shift register in a single cycle for replacing prior information located therewithin, gating means coupled with said loop circuit for selectively coupling the sum output of said adder into said register and for selectively coupling mantissa information from the second digital register into said shift register for arithmetic operation thereupon in said loop circuit including said adder, timing means for successively shifting information in said shift register and exponent means for receiving first and second exponent inputs and selectively providing an algebraic addition of the two, and the larger of the two, and counter means receiving the output of the exponent means, said timing means for shifting information in said shift register being coupled for selectively incrementing or decrementing the contents of said counter means in accordance with the shifting direction of said shift register.

Claim 24

A floating point system for providing a plurality of arithmetic operations and adapted for coupling to a computer comprising: a first digital register, a second digital register, a loop circuit including a shift register and an adder wherein said adder is coupled to receive a mantissa input from the first digital register for adding the same to the output of said shift register as received in said loop circuit, while providing a sum output in said loop circuit for entry back into said shift register in a single cycle for replacing prior information located therewithin, gating means coupled with said loop circuit for selectively coupling the sum output of said adder into said register and for selectively coupling mantissa information from the second digital register into said shift register for arithmetic operation thereupon in said loop circuit including said adder, timing means for successively shifting information in said shift register and exponent means for receiving first and second exponent inputs and selectively providing an algebraic addition of the two, and the larger of the two, and counter means receiving the output of the exponent means, said timing means for shifting information in said shift register being coupled for selectively incrementing or decrementing the contents of said counter means in accordance with the shifting direction of said shift register.

Claim 25

A floating point system for providing a plurality of arithmetic operations and adapted for coupling to a computer comprising: a first digital register, a second digital register, a loop circuit including a shift register and an adder wherein said adder is coupled to receive a mantissa input from the first digital register for adding the same to the output of said shift register as received in said loop circuit, while providing a sum output in said loop circuit for entry back into said shift register in a single cycle for replacing prior information located therewithin, gating means coupled with said loop circuit for selectively coupling the sum output of said adder into said register and for selectively coupling mantissa information from the second digital register into said shift register for arithmetic operation thereupon in said loop circuit including said adder, and timing means for successively shifting information in said shift register while controlling successive addition operations in said adder in response to the presence of successive digits in said second digital register as a multiplier.

Claim 26

A floating point system for providing a plurality of arithmetic operations and adapted for coupling to a computer comprising: a first digital register, a second digital register, a loop circuit including a shift register and an adder wherein said adder is coupled to receive a mantissa input from the first digital register for adding the same to the output of said shift register as received in said loop circuit, while providing a sum output in said loop circuit for entry back into said shift register in a single cycle for replacing prior information located therewithin, gating means coupled with said loop circuit for selectively coupling the sum output of said adder into said register and for selectively coupling mantissa information from the second digital register into said shift register for arithmetic operation thereupon in said loop circuit including said adder, and timing means for successively shifting information in said shift register while controlling successive addition operations in said adder in response to the presence of successive digits in said second digital register as a multiplier.