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US4491749A
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Three-output level logic circuit
Assignee: Toshiba Corp
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Filing: 1983-03-23
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Granted: 1985-01-01
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Expires: 2003-03-23
Abstract
Abstract A three-output level logic circuit comprises an output stage and a drive stage for driving the output stage. The output stage includes first and second MOS transistors connected in series between first and second power sources and a terminal is provided for producing three-state output signals. The drive stage includes third to sixth MOS transistors connected in series between the first and second power sources. A terminal is provided for supplying a data signal to the fourth and fifth MOS transistors. A control signal is supplied in common to the gate electrodes of the third to sixth MOS transistors. The conductivity types of the first to sixth MOS transistors are selected to operate the logic circuit with one control signal input and one data signal input.
Inventors
- 👤 Jun Iwamura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:25
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
194 words
A three-output level logic circuit comprising an output stage including an output terminal for selectively sending forth one of three outputs having different logic levels, a first metal oxide semiconductor (MOS) transistor of first conductivity type whose source-drain path is connected between said output terminal and a first power source, and a second MOS transistor of second conductivity type whose source-drain path is connected between said output terminal and a second power source; a drive stage for driving said output stage; and coupling means for coupling said output stage with said drive stage, wherein said drive stage comprises third and fourth MOS transistors of different conductivity types whose source-drain paths are connected in series between one of said first and second power sources and a data supply terminal, the gate electrodes of said third and fourth MOS transistors being supplied with a common control signal; and fifth and sixth MOS transistors of different conductivity types whose source-drain paths are connected in series between the other of said first and second power sources and said data supply terminal, the gate electrodes of said fifth and sixth MOS transistors being supplied with said common control signal.
Claim 2
Dependent Claim
194 words
A three-output level logic circuit comprising an output stage including an output terminal for selectively sending forth one of three outputs having different logic levels, a first metal oxide semiconductor (MOS) transistor of first conductivity type whose source-drain path is connected between said output terminal and a first power source, and a second MOS transistor of second conductivity type whose source-drain path is connected between said output terminal and a second power source; a drive stage for driving said output stage; and coupling means for coupling said output stage with said drive stage, wherein said drive stage comprises third and fourth MOS transistors of different conductivity types whose source-drain paths are connected in series between one of said first and second power sources and a data supply terminal, the gate electrodes of said third and fourth MOS transistors being supplied with a common control signal; and fifth and sixth MOS transistors of different conductivity types whose source-drain paths are connected in series between the other of said first and second power sources and said data supply terminal, the gate electrodes of said fifth and sixth MOS transistors being supplied with said common control signal.
Claim 3
Dependent Claim
68 words
The three-output level logic circuit according to claim 1, wherein said coupling means comprises means for directly connecting the common connecting node between the source-drain paths of said third and fourth MOS transistors to the gate electrode of the first MOS transistor, and also the common connecting node between the source-drain paths of said fifth and sixth MOS transistors to the gate electrode of the second MOS transistor.
Claim 4
Dependent Claim
70 words
The three-output level logic circuit according to claim 1, wherein said coupling means comprises inverting buffer means connected between the common connecting node between the source-drain paths of said third and fourth MOS transistors and the gate electrode of said first MOS transistor, and connected between the common connecting node between the source-drain paths of said fifth and sixth MOS transistors and the gate electrode of said second MOS transistor.
Claim 5
Dependent Claim
70 words
The three-output level logic circuit according to claim 1, wherein said coupling means comprises noninverting buffer means connected between the common connecting node between the source-drain paths of said third and fourth MOS transistors and the gate electrode of said first MOS transistor, and connected between the common connecting node between the source-drain paths of said fifth and sixth MOS transistors and the gate electrode of said second MOS transistor.
Claim 6
Dependent Claim
120 words
The three-output level logic circuit according to claim 1, wherein said third MOS transistor is an MOS transistor of first conductivity type whose source-drain path is connected at one end to one of said first and second power sources; said fourth MOS transistor is an MOS transistor of second conductivity type whose source-drain path is connected at one end to said data supply terminal; said fifth MOS transistor is an MOS transistor of second conductivity type whose source-drain path is connected at one end to said data supply terminal; and said sixth MOS transistor is an MOS transistor of first conductivity type whose source-drain path is connected at one end to the other of said first and second power sources.
Claim 7
Dependent Claim
111 words
The three-output level logic circuit according to claim 1, wherein said third MOS transistor is an MOS transistor of second conductivity type whose source-drain path is connected at one end to said first power source; said fourth MOS transistor is an MOS transistor of first conductivity type whose source-drain path is connected at one end to said data supply terminal; said fifth MOS transistor is an MOS transistor of first conductivity type whose source-drain path is connected at one end to said data supply terminal; and said sixth MOS transistor is an MOS transistor of second conductivity type whose source-drain path is connected at one end to said second power source.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-01 | 1988-07-02 | 1989-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-01 | 1992-07-02 | 1993-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-01 | 1996-07-02 | 1997-01-01 | $7700.00 | Window Closed / Lapsed |