Complementary mos logic circuit

Abstract

Abstract PURPOSE:To minimize the transition voltage value as well as to reduce the rise and fall time of the output for the complementary MOS logic circuit which is used at the master and slave parts of the master/slave flip-flop. CONSTITUTION:First complementary MOS transistor circuits 12 and 14 whose common gate terminal is connected to clock line 5 are connected between input terminal 7 and the first-level potential source (earth). And second complementary MOS transistor circuits 10 and 13 whose common gate terminal is connected to clock line 6 are connected between terminal 7 and second-level potential source VDD. Furthermore, output 17 of circuits 12 and 14 is applied to one gate of thrid complementary MOS transistor circuits 11 and 15, and output 16 of circuits 10 and 13 is applied to the other gate respectively. And the common drain terminal of circuits 11 and 15 is used as output terminal 8.

Inventors

• 👤 Toshiyuki Araki
• 👤 Takeshi Tokuda

Bibliographic Details