US4490819A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Rate converter
Assignee: Nokia of America Corp
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Filing: 1982-04-22
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Granted: 1984-12-25
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Expires: 2002-04-22
Abstract
Abstract A line switch for a digital telephone switching system utilizes distributed processing. The line switch comprises one or more switch modules. Each switch module is coupled to a central office switching system via one or more PCM lines which utilize common channel signaling. Each switch module comprises groups of line circuits, each line circuit being coupled to a subscriber line. Three separate distributed processor functions are provided in each line switch module. A first processor is utilized to communicate with the central office switching system and to coordinate the operations within the line switch module. A second processor is provided to control clock generation and rate conversion circuits. Each group of line circuits includes a third processor to control the operations of the line circuits and to gather information from the line circuit. A busing arrangement is provided within the line switch such that both control information and PCM voice data are routed throughout the line switch. The bus arrangement operates at a data rate higher than that of the PCM lines. A rate converter serves to interface two PCM lines to an internal PCM bus by interleaving channels from the two PCM lines onto the PCM bus and by further providing an additional control channel on the PCM bus. The rate converter further serves to demultiplex channels from the PCM bus onto the PCM lines.
Inventors
- 👤 Leonard E. Bogan
- 👤 Paul H. Knapke
- 👤 Robert L. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:21
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/05
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
296 words
A rate conversion arrangement for interfacing first and second time-division multiplex lines each operating at a first data rate to a time-division multiplexed bus operating at a second data rate, said second data rate being a multiple of said first data rate, each of said lines carrying a plurality of frame organized PCM channels each frame having a first number of channels, each of said channels comprising a predetermined number of data bits, said arrangement comprising: first memory means for storing data bits; second memory means for storing data bits; first receiving means for receiving first data bits from said first line at said first data rate; second receiving means for receiving second data bits from said second line at said first data rate; first storing means for storing said first data bits in said first memory means; second storing means for storing said second data bits in said second memory means; first reading means for reading said stored first data bits for one channel from said memory means; second reading means for reading said stored second data bits for another channel from said second memory means; means for transmitting said read first data bits and said read second data bits over said bus at said second data rate, said read first data bits for said one channel and said read second data bits for said another channel being transmitted in a predetermined sequence; and second means for receiving data bits at said second rate from said bus and for transmitting data bits from first predetermined channels of said bus in sequential channels of said first line at said first data rate and for transmitting data bits from other predetermined channels of said bus in sequential channels of said second line at said first data rate.
Claim 2
Dependent Claim
296 words
A rate conversion arrangement for interfacing first and second time-division multiplex lines each operating at a first data rate to a time-division multiplexed bus operating at a second data rate, said second data rate being a multiple of said first data rate, each of said lines carrying a plurality of frame organized PCM channels each frame having a first number of channels, each of said channels comprising a predetermined number of data bits, said arrangement comprising: first memory means for storing data bits; second memory means for storing data bits; first receiving means for receiving first data bits from said first line at said first data rate; second receiving means for receiving second data bits from said second line at said first data rate; first storing means for storing said first data bits in said first memory means; second storing means for storing said second data bits in said second memory means; first reading means for reading said stored first data bits for one channel from said memory means; second reading means for reading said stored second data bits for another channel from said second memory means; means for transmitting said read first data bits and said read second data bits over said bus at said second data rate, said read first data bits for said one channel and said read second data bits for said another channel being transmitted in a predetermined sequence; and second means for receiving data bits at said second rate from said bus and for transmitting data bits from first predetermined channels of said bus in sequential channels of said first line at said first data rate and for transmitting data bits from other predetermined channels of said bus in sequential channels of said second line at said first data rate.
Claim 3
Dependent Claim
161 words
An arrangement in accordance with claim 1, wherein said second means comprises: third memory means for storing data bits; fourth memory means for storing data bits; third receiving means coupled to said bus receiving third data bits from said first predetermined channels at said second rate; fourth receiving means coupled to said bus for receiving fourth data bits from said other predetermined channels at said second rate; third storing means for storing said received third data bits in said third memory means; fourth storing means for storing said received fourth data bits in said fourth memory means; third reading means for reading said stored third data bits from said third memory means; fourth reading means for reading said stored fourth data bits from said fourth memory means; third transmitting means for transmitting said read third data bits over said first line at said first data rate; and fourth transmitting means for transmitting said read fourth data bits over said second line.
Claim 4
Dependent Claim
43 words
An arrangement in accordance with claim 1, wherein predetermined ones of said frames received on said first and second lines include one or more bits of first predetermined information, said arrangement comprising means for extracting said one or more bits of predetermined information.
Claim 5
Dependent Claim
52 words
An arrangement in accordance with claim 2, further comprising: means for inserting one or more bits of second predetermined information in predetermined ones of said frames on said first line; and means for inserting one or more bits of second predetermined information in predetermined ones of said frames on said second line.
Claim 6
Dependent Claim
43 words
An arrangement in accordance with claim 4, wherein predetermined onees of said frames received on said first and second lines include one or more bits of first predetermined information, said arrangement comprising means for extracting said one or more bits of predetermined information.
Claim 7
Dependent Claim
18 words
An arrangement in accordance with claim 4, wherein said second predetermined information comprises common channel or signalling information.
Claim 8
Dependent Claim
21 words
An arrangement in accordance with claims 3, 4, or 5, wherein said first predetermined information comprises common channel or signalling information.
Claim 9
Dependent Claim
268 words
A rate conversion arrangement comprising: first and second time-division multiplex lines, each operating at a first data rate, each of said lines carrying a first plurality of frame organized first channels, each frame of said first plurality of frames having a plurality of first channels, each of said first channels comprising a first predetermined number of data bits, a time-division multiplexed bus operating at a second data rate, said second data rate being a multiple of said first data rate, said bus carrying a second plurality of frame organized channels, each frame of said second plurality of frames having a plurality of second channels, each of said second channels comprising a second predetermined number of data bits; first memory means coupled to said bus for storing second channel data bits; second memory means coupled to said bus for storing second channel data bits; first storing means coupled to said first memory means for causing said first memory means to store second channel data bits from first predetermined ones of said second channels; second storing means coupled to said second memory means for causing said second memory means to store second channel data bits from other predetermined ones of said second channels; first means for reading said second channel data bits stored in said first memory means and for transmitting said data bits from said first memory over said first line at said first rate; and second means for reading said second channel data bits stored in said second memory means and for transmitting said data bits from said second memory over said second line at said first rate.
Claim 10
Dependent Claim
268 words
A rate conversion arrangement comprising: first and second time-division multiplex lines, each operating at a first data rate, each of said lines carrying a first plurality of frame organized first channels, each frame of said first plurality of frames having a plurality of first channels, each of said first channels comprising a first predetermined number of data bits, a time-division multiplexed bus operating at a second data rate, said second data rate being a multiple of said first data rate, said bus carrying a second plurality of frame organized channels, each frame of said second plurality of frames having a plurality of second channels, each of said second channels comprising a second predetermined number of data bits; first memory means coupled to said bus for storing second channel data bits; second memory means coupled to said bus for storing second channel data bits; first storing means coupled to said first memory means for causing said first memory means to store second channel data bits from first predetermined ones of said second channels; second storing means coupled to said second memory means for causing said second memory means to store second channel data bits from other predetermined ones of said second channels; first means for reading said second channel data bits stored in said first memory means and for transmitting said data bits from said first memory over said first line at said first rate; and second means for reading said second channel data bits stored in said second memory means and for transmitting said data bits from said second memory over said second line at said first rate.
Claim 11
Dependent Claim
20 words
An arrangement in accordance with claim 8, wherein said second data rate is greater than twice said first data rate.
Claim 12
Dependent Claim
42 words
An arrangement in accordance with claim 9, wherein the number of said first channels in each frame of said first plurality of frames is "n"; and the number of second channels in each frame of said second plurality of frames is "2n".
Claim 13
Dependent Claim
27 words
An arrangement in accordance with claim 10, wherein each frame of said second plurality of frames further comprises one or more additional channels for carrying other information.
Claim 14
Dependent Claim
40 words
An arrangement in accordance with claim 11, further comprising: clocking means for controlling said first and second memory means such that data bits of said one or more additional channels are not stored in said first and second memory means.
Claim 15
Dependent Claim
139 words
An arrangement in accordance with claim 8, further comprising: third memory means coupled to said first line for storing said first channel data bits; fourth memory means coupled to said second line for storing said first channel data bits; third storing means coupled to said third memory means for causing said third memory means to store first channel data bits from said first line at said first data rate; fourth storing means coupled to said fourth memory means for causing said fourth memory means to store first channel data bits from said second line at said first data rate; and third reading means for reading said stored first channel data bits from said third and fourth memory means and for transmitting said stored first channel data bits in a predetermined sequence at said second data rate over said bus.
Claim 16
Dependent Claim
51 words
An arrangement in accordance with claim 13, wherein said predetermined sequence comprises transmitting said stored first channel data bits from said third memory means in alternate ones of said second channels and transmitting said stored first channel data bits from said fourth memory means in intermediate ones of said second channel.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-25 | 1988-06-25 | 1988-12-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-25 | 1992-06-25 | 1992-12-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-25 | 1996-06-25 | 1996-12-25 | $7700.00 | Window Closed / Lapsed |