US4402079A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Delay correction circuit
Assignee: Nokia of America Corp
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Filing: 1980-10-24
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Granted: 1983-08-30
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Expires: 2000-10-24
Abstract
Abstract A delay correction circuit is described for use with an elastic store in a PCM time division multiplexed system. The relative position of the read and write addresses supplied to the elastic store are monitored. In the event that either the read or write addresses are overtaking the other and are within a predetermined range of addresses, either the read or write address source will be initialized at a predetermined time such that the read and write addresses have new relative position.
Inventors
- 👤 Frank Fellinger
- 👤 James M. Ruffing
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 16:39
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04J; H04J3/00; H04J3/16; H04J3/1605; H04J3/1623; H04J3/1635; H04L; H04L25/00; H04L25/02; H04L25/05
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
237 words
A delay correction circuit for use with an elastic store in a time division multiplexed system wherein said elastic store comprises memory means for storing incoming data bits, write address generating means for generating write addresses, each of said write addresses identifying a location in said memory means for storing an incoming data bit, and read address generating means for identifying a location in said memory means for reading a stored data bit, said delay correction circuit comprising: first means responsive to one of said read or write address generating means generating a predetermined address for determining whether the address concurrently generated by the other of said read or write address generating means is within a predetermined range of addresses and for providing a first indication signal if said concurrently generated address leads said predetermined address and a second indication signal if said concurrently generated address lags said predetermined address; second means responsive to said first indication signal and the generation of a second predetermined address by one of said read or write address generating means for initializing the other of said read or write address generating means to a third predetermined address; and third means responsive to said second indication signal and the generation of a fourth predetermined address by one of said read or write address generating means for initializing the other of said read or write address generating means to a fifth predetermined address.
Claim 2
Dependent Claim
237 words
A delay correction circuit for use with an elastic store in a time division multiplexed system wherein said elastic store comprises memory means for storing incoming data bits, write address generating means for generating write addresses, each of said write addresses identifying a location in said memory means for storing an incoming data bit, and read address generating means for identifying a location in said memory means for reading a stored data bit, said delay correction circuit comprising: first means responsive to one of said read or write address generating means generating a predetermined address for determining whether the address concurrently generated by the other of said read or write address generating means is within a predetermined range of addresses and for providing a first indication signal if said concurrently generated address leads said predetermined address and a second indication signal if said concurrently generated address lags said predetermined address; second means responsive to said first indication signal and the generation of a second predetermined address by one of said read or write address generating means for initializing the other of said read or write address generating means to a third predetermined address; and third means responsive to said second indication signal and the generation of a fourth predetermined address by one of said read or write address generating means for initializing the other of said read or write address generating means to a fifth predetermined address.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-08-29 | 1987-02-28 | 1987-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-08-29 | 1991-02-28 | 1991-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-08-29 | 1995-02-28 | 1995-08-30 | $7700.00 | Window Closed / Lapsed |