US4058682A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Expandable memory for PCM signal transmission
Assignee: Italtel SpA
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Filing: 1976-06-04
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Granted: 1977-11-15
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Expires: 1996-06-04
Abstract
Abstract An incoming bit stream of a first bit frequency, divided into a succession of n-bit words, is converted into an outgoing bit stream of a second bit frequency with the aid of two n-stage buffer registers alternately loaded by two sets of interleaved writing pulses, on every n th cycle of the first bit frequency, with incoming words which are alternately read out on every n th cycle of the second bit frequency by two sets of interleaved reading pulses. A logic network detects the coincidence of a reading pulse from one set with either of two guard pulses immediately preceding and succeeding, respectively, each writing pulse of the corresponding set; upon such coincidence, a switching network transposes the two sets of writing pulses to restore an original relative pulse position in which the reading pulses of each set occur substantially midway between writing pulses of the same set.
Inventors
- 👤 Roberto Delle Donne
- 👤 Luigi Musumeci
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 15:27
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626; H04Q; H04Q11/00; H04Q11/04
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
289 words
An expandable memory for converting an incoming bit stream of a first bit frequency, divided into a succession of n-bit words where n is an integer greater than 2, into an outgoing bit stream of a second bit frequency, comprising: first timing means controlled by the incoming bit stream for generating on a first pair of outputs a pair of interleaved pulse trains of a cadence 1/2n times said first bit frequency; second timing means independent of said incoming bit stream for generating on a second pair of outputs a second pair of interleaved pulse trains of a cadence 1/2n times said second bit frequency, the pulses of each train of said second pair being normally spaced from the pulses of corresponding trains of said first pair; bit-storing means including a pair of n-stage buffer registers, with writing inputs respectively connected to said first pair of outputs and with reading inputs respectively connected to said second pair of outputs; first circuit means for alternately writing the words of said incoming bit stream into said buffer registers under the control of said first pair of pulse trains; second circuit means for alternately reading the words written in said buffer registers under the control of said second pair of pulse trains; monitoring means connected to said first and second circuit means for detecting a near-coincidence of a pulse from one of said second pair of pulse trains with a pulse from the corresponding one of said first pair of pulse trains; and switchover means controlled by said monitoring means for transposing the pulse trains on one of said pairs of outputs, thereby re-establishing a normal spacing between the pulses of corresponding trains of said first and second pairs of pulse trains.
Claim 2
Dependent Claim
289 words
An expandable memory for converting an incoming bit stream of a first bit frequency, divided into a succession of n-bit words where n is an integer greater than 2, into an outgoing bit stream of a second bit frequency, comprising: first timing means controlled by the incoming bit stream for generating on a first pair of outputs a pair of interleaved pulse trains of a cadence 1/2n times said first bit frequency; second timing means independent of said incoming bit stream for generating on a second pair of outputs a second pair of interleaved pulse trains of a cadence 1/2n times said second bit frequency, the pulses of each train of said second pair being normally spaced from the pulses of corresponding trains of said first pair; bit-storing means including a pair of n-stage buffer registers, with writing inputs respectively connected to said first pair of outputs and with reading inputs respectively connected to said second pair of outputs; first circuit means for alternately writing the words of said incoming bit stream into said buffer registers under the control of said first pair of pulse trains; second circuit means for alternately reading the words written in said buffer registers under the control of said second pair of pulse trains; monitoring means connected to said first and second circuit means for detecting a near-coincidence of a pulse from one of said second pair of pulse trains with a pulse from the corresponding one of said first pair of pulse trains; and switchover means controlled by said monitoring means for transposing the pulse trains on one of said pairs of outputs, thereby re-establishing a normal spacing between the pulses of corresponding trains of said first and second pairs of pulse trains.
Claim 3
Dependent Claim
26 words
An expandable memory as defined in claim 1 wherein said first circuit means comprises a series/parallel converter and said second circuit means comprises a parallel/series converter.
Claim 4
Dependent Claim
31 words
An expandable memory as defined in claim 2 wherein said bit-storing means further comprises a multiplexer provided with said reading inputs and inserted between said buffer registers and said parallel/series converter.
Claim 5
Dependent Claim
88 words
An expandable memory as defined in claim 1 wherein one of said timing means has outputs producing a first and a second guard pulse immediately before and immediately after each pulse of one of the trains of the respective pair of pulse trains, said monitoring means comprising a logic network connected to said outputs for generating a transposition command for said switchover means in response to a coincidence of either of said guard pulses with a pulse of the corresponding train of the other pair of pulse trains.
Claim 6
Dependent Claim
34 words
An expandable memory as defined in claim 4 wherein said one of said timing means is said first timing means, said switchover means being inserted between said first timing means and said writing inputs.
Claim 7
Dependent Claim
43 words
An expandable memory as defined in claim 4 wherein said logic network includes storage means for temporarily preserving said transposition command, and a source of periodic test pulses connected to said storage means for forwarding a stored transposition command to said switchover means.
Claim 8
Dependent Claim
36 words
An expandable memory as defined in claim 6 wherein said source is coupled with said second timing means for producing said test pulses at a submultiple of the cadence of said second pair of pulse trains.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-11-14 | 1981-05-16 | 1981-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-11-14 | 1985-05-16 | 1985-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-11-14 | 1989-05-16 | 1989-11-15 | $7700.00 | Window Closed / Lapsed |