Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
82 words
A transition coincidence detection and compensation circuit for a synchronous digital data transmission system wherein data is transmitted and received between a central system device and a remote terminal, said circuit comprising a circuit connected to detect transition coincidence between data received by the central device from the remote terminal and a local system clock and circuit means responsive to said circuit to delay said outgoing data from said device, upon which outgoing data the timing of said received data is dependent.
Claim 2
Dependent Claim
82 words
A transition coincidence detection and compensation circuit for a synchronous digital data transmission system wherein data is transmitted and received between a central system device and a remote terminal, said circuit comprising a circuit connected to detect transition coincidence between data received by the central device from the remote terminal and a local system clock and circuit means responsive to said circuit to delay said outgoing data from said device, upon which outgoing data the timing of said received data is dependent.
Claim 3
Dependent Claim
83 words
A transition coincidence detection and compensation circuit as defined in claim 1 wherein said circuit is adapted to provide an output when a transition of said rEceived data occurs and a strobe pulse is present in said circuit, said strobe pulse being related to said local system clock and being timed to be present during the time when said received data may be lost because of a transition coincidence with said local clock, said circuit output affecting a delay in said outgoing data.
Claim 4
Dependent Claim
58 words
A transition coincidence detection and compensation circuit as defined in claim 2 wherein the repetition rate of said strobe pulse is equal to or less than the system clock repetition rate divided by the maximum propogation delay in a loop circuit, between said central system device and said remote terminal including any resynchronisation delay in said remote terminal.
Claim 5
Dependent Claim
58 words
A transition coincidence detection and compensation circuit as defined in claim 3 wherein said circuit means responsive to said circuit is locked in position to delay said outgoing data when said detection occurs unless a further transition coincidence is detected, in which case the circuit means reverts to its original form whereby the outgoing data is not delayed.
Claim 6
Dependent Claim
42 words
A transition coincidence detection and compensation circuit as defined in claim 4 wherein said delay is effected by clocking the outgoing data with a clock signal which is 180 out of phase with the normal clock signal used to clock outgoing data.
Claim 7
Dependent Claim
81 words
A transition coincidence detection and compensation circuit as defined in claim 5 wherein said circuit comprises a +ve edge triggered flip-flop which is clocked by said received data, and an exclusive OR gate through which said strobe pulse is supplied to the data input of said flip-flop, the set output of the flip-flop providing said circuit output when said strobe pulse is present at the data input of the flip-flop during the time when said flip-flop is clocked by the data.
Claim 8
Dependent Claim
75 words
A transition coincidence detection and compensation circuit as defined in claim 6 wherein outgoing data is diphased data which is clocked through an outgoing + or - ve edge triggered flip-flop at twice the normal data rate, the clock for said outgoing data being fed through a further exclusive OR gate and said circuit output being fed to said further OR gate to invert the clock for said outgoing data when said transition coincidence occurs.
Claim 9
Dependent Claim
45 words
A transition coincidence detection and compensation circuit as defined in claim 7 wherein said system is a synchronous digital telephone system, said central system device being the switch or exchange of the system and said remote terminal being one of the telephones of the system.