Patent US4489247A successfully refreshed from Google Patents.
US4489247A
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Integrated injection logic circuit with test pads on injector common line
Assignee: Toshiba Corp
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Filing: 1982-02-17
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Granted: 1984-12-18
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Expires: 2002-02-17
Abstract
Abstract An integrated injection logic circuit includes a plurality of integrated injection logic gates each having a PNP transistor for injector and NPN transistor for signal inversion, and an injector common line to which the respective injector PNP transistors are commonly connected. A test pad for electric probing is provided at least one location of the injector common line.
Inventors
- 👤 Masashi Ikeda
- 👤 Yukuya Tokumaru
- 👤 Masanori Nakai
- 👤 Masaki Ota
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:27
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31712; G01R31/31715; H; H10; H10D; H10D84/00; H10D84/60; H10D84/65
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
50 words
An integrated injection logic circuit comprising: a plurality of integrated injection logic gates having injector means; an injector common line to which the injector means of the respective integrated injection logic gates are commonly connected; and at least two test pads for electric probing provided on the injector common line.
Claim 2
Dependent Claim
50 words
An integrated injection logic circuit comprising: a plurality of integrated injection logic gates having injector means; an injector common line to which the injector means of the respective integrated injection logic gates are commonly connected; and at least two test pads for electric probing provided on the injector common line.
Claim 3
Dependent Claim
24 words
An integrated injection logic circuit according to claim 1, in which said test pads are provided at the ends of said injector common line.
Claim 4
Dependent Claim
18 words
An integrated injection logic circuit according to claim 1, in which said injector means includes a PNP transistor.
Claim 5
Dependent Claim
24 words
An integrated injection logic circuit according to claim 1, in which said test pads include an increased width portion of said injector common line.
Claim 6
Dependent Claim
58 words
An integrated injection logic circuit comprising: a plurality of integrated injection logic gates each having injector means; a plurality of injector common lines to each of which a predetermined number of said plurality of integrated injection logic gates are commonly connected; and at least two test pads for electric probing provided on each of the injector common lines.
Claim 7
Dependent Claim
58 words
An integrated injection logic circuit comprising: a plurality of integrated injection logic gates each having injector means; a plurality of injector common lines to each of which a predetermined number of said plurality of integrated injection logic gates are commonly connected; and at least two test pads for electric probing provided on each of the injector common lines.
Claim 8
Dependent Claim
26 words
An integrated injection logic circuit according to claim 5, in which said test pads are provided at the ends of each of said injector common lines.
Claim 9
Dependent Claim
18 words
An integrated injection logic circuit according to claim 5, in which said injector means includes a PNP transistor.
Claim 10
Dependent Claim
24 words
An integrated injection logic circuit according to claim 5, in which said test pads include an increased width portion of said injector common line.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-12-18 | 1988-06-18 | 1988-12-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-12-18 | 1992-06-18 | 1992-12-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-12-18 | 1996-06-18 | 1996-12-18 | $7700.00 | Window Closed / Lapsed |