Multi-computer system having dual common memory

Claim 2

A multi-computer system comprising a plurality of computers each of which has a central processing unit and a dual memory access unit; at least two common memories; interface means for connecting the dual memory access units in all of said computers to each of said common memories; and maintenance demand appointing means connected to said common memories for providing a maintenance demand signal to the dual memory access unit in at least one of said computers when an error occurs in connection with a memory access; at least one of the central processing units including maintenance flag means for producing a maintenance program appointing signal when a maintenance program is to be executed in this central processing unit and each of said common memories having at least one status means for producing a status signal representing whether or not the common memory is in a normal operating condition; said dual memory access unit in each central processing unit including means responsive to said maintenance program appointing signal for restricting access by that central processing unit to the common memory selected by said maintenance demand signal and identified by a status signal representing that the common memory is not in a normal operating condition for executing a maintenance program in connection with that common memory.

Claim 3

A multi-computer system comprising a plurality of computers each of which has a central processing unit, a main memory and a dual memory access unit; at least two common memories each of which has a memory unit, a memory controller and a plurality of computer ports each corresponding to one of said plurality of computers; interface means for connecting respective computer ports to said dual memory access units of the corresponding computers; and maintenance demand appointing means for providing maintenance demand signals for the respective common memories; at least one of said central processing units having maintenance flag means for producing a maintenance program appointing signal when a maintenance program is to be executed in this central processing unit and common memory flag means for producing a common memory appointing signal when the contents of the common memory are required to be read or when data is to be written therein; said memory controller for each common memory having at least status means for producing a status signal representing that the memory unit is not in a normal operating condition; and said dual memory access unit in each central processing unit including means responsive to said maintenance program appointing signal for restricting access by a central processing unit to a common memory which is determined by the common memory appointing signal, maintenance demand signal and the status signal representing that the common memory is not in a normal operating condition for executing a maintenance program in connection with that common memory.

Claim 4

A multi-computer system comprising a plurality of computers each of which has a central processing unit, a main memory and a dual memory access unit; at least two common memories each of which has a memory unit, a memory controller and a plurality of computer ports each corresponding to one of said plurality of computers; interface means for connecting respective computer ports to said dual memory access units of the corresponding computers; and maintenance demand appointing means for providing maintenance demand signals for the respective common memories; at least one of said central processing units having maintenance flag means for producing a maintenance program appointing signal when a maintenance program is to be executed in this central processing unit and common memory flag means for producing a common memory appointing signal when the contents of the common memory are required to be read or when data is to be written therein; said memory controller for each common memory having at least status means for producing a status signal representing that the memory unit is not in a normal operating condition; and said dual memory access unit in each central processing unit including means responsive to said maintenance program appointing signal for restricting access by a central processing unit to a common memory which is determined by the common memory appointing signal, maintenance demand signal and the status signal representing that the common memory is not in a normal operating condition for executing a maintenance program in connection with that common memory.

Claim 5

A multi-computer system according to claim 2, wherein each memory controller includes register means for storing data received from the associated memory unit, means for applying the data in said register means to a given computer via the associated computer port, and parity check means for checking the parity of the data in said register means and for generating said status signal.

Claim 6

A multi-computer system according to claim 3, wherein said maintenance demand appointing means includes indicator means responsive to an error signal for providing a visual indication of a detected error and manually operated switch means for generating a maintenance demand signal.

Claim 7

A multi-computer system according to claim 4, wherein each memory controller includes memory status controller means responsive to an error signal for applying a maintenance demand signal generated by said switch means through a computer port to the associated computer.

Claim 8

A multi-computer system according to claim 2, wherein said maintenance demand appointing means includes memory status controller means responsive to an error signal from a memory controller for applying a maintenance demand signal through a computer port to a selected computer.

Claim 9

A multi-computer system according to claim 2, wherein said memory access controller means includes means for generating first and second enabling signals individually or simultaneously for enabling a computer port of one or both of said common memories in response to the signals applied to said memory access controller means.