Voltage level shifting circuit

Claim 2

A voltage level shifting circuit comprising: an input node and an output node; a first transistor for controllably clamping the output node to a first voltage level and having a control electrode coupled to the input node; a second transistor for controllably clamping the output node to a second voltage level and having a control electrode coupled to the input node; a third transistor for controllably providing the second voltage level to the input node and having a control electrode coupled to the output node; a fourth transistor in parallel with the first transistor for assisting the first transistor to clamp the output node to the first voltage level and having a control electrode coupled to the input node; and a fifth transistor for controllably holding the control electrode of the first transistor to the first voltage level and having a control electrode coupled to the output node.

Claim 3

The level shift circuit of claim 1 further having means for dropping voltage coupled in series between the control electrode of the first transistor and the input node, and means coupled in series with the fourth transistor to increase the threshold voltage of the fourth transistor.

Claim 4

The level shift circuit of claim 2 wherein the means for dropping is a diode, and the means coupled in series is a diode connected N-channel field effect transistor.

Claim 5

An interface circuit for interfacing a TTL circuit to a CMOS circuit, the interface circuit having an input node and an output node and comprising: first means for controllably coupling the output node to a first voltage conductor and being controlled by a signal present at the input node; second means for controllably coupling the output node to a second voltage conductor and being controlled by the signal present at the input node; third means for controllably coupling the input node to the first voltage conductor and being controlled by an output present at the output node wherein the first and third means have a first threshold voltage and the second means has a second threshold voltage; and fourth means coupled in parallel with the second means to controllably provide better coupling between the output node and the second voltage conductor and being controlled by the signal present at the input node.

Claim 6

An interface circuit for interfacing a TTL circuit to a CMOS circuit, the interface circuit having an input node and an output node and comprising: first means for controllably coupling the output node to a first voltage conductor and being controlled by a signal present at the input node; second means for controllably coupling the output node to a second voltage conductor and being controlled by the signal present at the input node; third means for controllably coupling the input node to the first voltage conductor and being controlled by an output present at the output node wherein the first and third means have a first threshold voltage and the second means has a second threshold voltage; and fourth means coupled in parallel with the second means to controllably provide better coupling between the output node and the second voltage conductor and being controlled by the signal present at the input node.

Claim 7

A level shift circuit having an input node, an output node, and comprising: a first P-channel FET having a first current electrode coupled to a first voltage terminal and a second current electrode coupled to the output node and a control electrode coupled to the input node; a first and a second N-channel FET each having a first current electrode coupled to the output node, a second current electrode coupled to a second voltage terminal, and a control electrode coupled to the input node; a third N-channel FET having a first current electrode coupled to the control electrode of the second N-channel FET, a second current electrode coupled to the second voltage terminal, and a control electrode coupled to the output node to bias off the second N-channel FET when the output node is at a predetermined voltage; and a second P-channel FET having a first current electrode coupled to the first voltage terminal, a second current electrode coupled to the input node, and a control electrode coupled to the output node to maintain the input node at a high logic level when the output node is at a low logic level.

Claim 8

A level shift circuit having an input node, an output node, and comprising: a first P-channel FET having a first current electrode coupled to a first voltage terminal and a second current electrode coupled to the output node and a control electrode coupled to the input node; a first and a second N-channel FET each having a first current electrode coupled to the output node, a second current electrode coupled to a second voltage terminal, and a control electrode coupled to the input node; a third N-channel FET having a first current electrode coupled to the control electrode of the second N-channel FET, a second current electrode coupled to the second voltage terminal, and a control electrode coupled to the output node to bias off the second N-channel FET when the output node is at a predetermined voltage; and a second P-channel FET having a first current electrode coupled to the first voltage terminal, a second current electrode coupled to the input node, and a control electrode coupled to the output node to maintain the input node at a high logic level when the output node is at a low logic level.

Claim 9

The level shift circuit of claim 5 further including a fourth N-channel FET coupled between the second current electrode of the first N-channel FET and the second voltage terminal, wherein the fourth N-channel FET has a first current electrode and a control electrode both coupled to the second current electrode of the first N-channel FET, and having a second current electrode coupled to the second voltage terminal; and diode means for coupling the control electrode of the second N channel FET to the input node.