Fet interface circuit

Claim 1

A self-biasing FET converter circuit for converting low voltage binary signals to higher voltage binary signals, said self-biasing FET converter circuit comprising: an input node; an output node; a signal FET with a first threshold voltage level having two gated electrodes and a gating electrode, and operatively connected to receive a low voltage binary input signal from said input node and providing a converted higher voltage binary output signal at said output node, said signal FET having high and low stable conducting states; a load FET having a common connection in series with said signal FET, said common connection being operatively connected to said output node; and a feedback FET with a second threshold voltage level being higher than said first threshold voltage level, having a gating electrode and first and second gated electrodes connected as a diode between said input node and said output node, the first gated electrode and said gating electrode being connected to said common connection, the second gated electrode being operatively connected to the gating electrode of said signal FET; the feedback FET providing a feedback path from the common connection to the gating electrode of the signal FET for biasing the gating electrode of the signal FET to a predetermined potential level, such that when said signal FET is in its low stable conducting state then the potential at its gating electrode differs by one threshold voltage drop from the potential level of the output node, thereby maintaining the potential level at the gating electrode of the signal FET slightly in excess of its threshold voltage drop when said signal FET is in its low stable conducting state.