Method for manufacturing an integrated circuit device

Claim 1

A method for manufacturing an integrated circuit device comprising the steps of: (A) processing a silicon circuit wafer (10) to form an integrated circuit (14) including an active circuit (19) and at least one alignment pattern (32) on a first surface of the circuit wafer; (B) surrounding at least a portion of the active circuit (19) with a barrier (24) to environmental contaminants by forming a moat (18); (C) placing a conductor (30) over the barrier (18, 24) placed in Step B to provide an interconnection between a selected location of the active circuit (19) and a selected contact surface (22) outside of the portion of the active circuit surrounded by the barrier (24); (D) preparing the surface of a support wafer (40) for subsequent processing; (E) positioning the first surface of the circuit wafer (10) opposing the first surface of the support wafer (40); (F) forming a layer of adhesive (46) on the opposing first surfaces of said circuit and support wafers (10, 40) so as to cause the two wafers to adhere together forming a wafer sandwich (50); (G) photoshaping an opening (47) through the circuit wafer (10) to expose indicia (32a) corresponding to the alignment pattern (32); (H) photoshaping the circuit wafer (10) using the indicia (32a) exposed in Step F to produce contact openings through the circuit wafer (10) to selected contact surfaces (22) of the integrated circuit (14); (I) preparing the contact surfaces (22) exposed in Step H; and (J) slicing the wafer sandwich (50) into a plurality of chips (72).

Claim 2

A method for manufacturing an integrated circuit device comprising the steps of: (A) processing a silicon circuit wafer (10) to form an integrated circuit (14) including an active circuit (19) and at least one alignment pattern (32) on a first surface of the circuit wafer; (B) surrounding at least a portion of the active circuit (19) with a barrier (24) to environmental contaminants by forming a moat (18); (C) placing a conductor (30) over the barrier (18, 24) placed in Step B to provide an interconnection between a selected location of the active circuit (19) and a selected contact surface (22) outside of the portion of the active circuit surrounded by the barrier (24); (D) preparing the surface of a support wafer (40) for subsequent processing; (E) positioning the first surface of the circuit wafer (10) opposing the first surface of the support wafer (40); (F) forming a layer of adhesive (46) on the opposing first surfaces of said circuit and support wafers (10, 40) so as to cause the two wafers to adhere together forming a wafer sandwich (50); (G) photoshaping an opening (47) through the circuit wafer (10) to expose indicia (32a) corresponding to the alignment pattern (32); (H) photoshaping the circuit wafer (10) using the indicia (32a) exposed in Step F to produce contact openings through the circuit wafer (10) to selected contact surfaces (22) of the integrated circuit (14); (I) preparing the contact surfaces (22) exposed in Step H; and (J) slicing the wafer sandwich (50) into a plurality of chips (72).