← Back to Patent Explorer
US3775838A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated circuit package and construction technique

Assignee: Olivetti SpA
•
Filing: 1972-04-24
•
Granted: 1973-12-04
•
Expires: 1992-04-24
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract Disclosed is an integrated circuit arrangement and construction technique wherein an improved circuit board, having deposited thereon resistors and conductors, is constructed by means of a combination of evaporation and electrodeposition techniques. A layer of resistive material and a layer of conductive material are successively deposited by means of evaporation onto a substrate. A third layer of conductive material is then deposited by means of electroplating. The construction process includes a high temperature stabilization phase, an improved resistor trim by means of electroerosion, and a semiconductor afixation phase which utilizes high temperature gas in conjunction with mechanical friction.

Inventors

  • 👤 C Dalmasso

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 20:20
CPC Classifications
H; H10; H10W; H10W99/00; H10D; H10D86/00; H10D86/80; H10D86/85; H10W90/00; H10W90/701; H10W90/751; H10W90/756; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913; Y10T29/49144

Claims Analysis

Total Claims: 3
Claim 1
Independent Claim 24 words
The process according to claim 1 wherein said conductive layers are of gold, said resistive layer is NiCr, and said insulative layer is ceramic.
Claim 2
Dependent Claim 18 words
The process according to claim 1 wherein said second conductive layer is 2.5 to 5 microns in thickness.
Claim 3
Dependent Claim 52 words
The process according to claim 1 comprising following said step of removing said first conductive layer and said resistive layer only from said second region, the additional step of: heating said circuit network in an inert atmosphere prior to said step of affixing said semiconductor circuit elements to said second conductive layer.

References Cited (Backward Citations)

US3488840A Cited
US3561107A Cited
US3470611A Cited
US3556951A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-12-03 1977-06-04 1977-12-04 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-12-03 1981-06-04 1981-12-04 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-12-03 1985-06-04 1985-12-04 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag