Corner turn memory address generator

Claim 1

Circuitry for generating an address sequence, each member of said address sequence specifying a storage location in a digital memory for storing data, said data being arranged as a data matrix having first and second dimensions designated as (M) columns and (N) rows, each element of said data matrix occupying at least one storage location in said memory with the product (M) (N) being an integral power of two, comprising in combination: (a) adder means having at least first and second data input terminals and data output terminals; (b) first storage means comprising a shift register having data input and data output terminals for storing a first digital number, said first digital number comprising a member of said address sequence to produce at said data output terminals said first digital number said storage means further comprising means operable to shift said shift register one bit each time the output signal of said adder means is equal to ((M×N)-1); (c) second storage means for storing a second number to be added to said first digital number to generate a second member of said address sequence; (d) third storage means having data input and data output terminals for storing the current member of said address sequence to produce at said data output terminals of said third storage means said current member of said address sequence; (e) circuit means for (1) coupling said first digital number to said first data input terminals of said adder means, (2) coupling means for coupling said second number to said second data input terminals of said adder, (3) coupling means for coupling said data output terminals of said adder means to said input data terminals of said first storage means, and (f) clock signal means for sequentially storing the output of said adder means in said third storage means, thereby producing sequential members of said address sequence at the output terminal of said third storage means.