US4080599A
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US
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Memory addressing apparatus and method
Assignee: Westinghouse Electric Corp
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Filing: 1976-07-28
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Granted: 1978-03-21
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Expires: 1996-07-28
Abstract
Abstract An improved corner turn memory addressing system and method for radar wherein digital data corresponding to the reflected value of each radar pulse for successive range gates is written in sequence, and such digital data for each range gate for succesive radar pulses is read out, in sequence, is disclosed. As each data item is read out of a selected address of a memory, a new received data item is written into the same address. A single data value is summed with each previous address to determine the subsequent address for each data item of a single radar "look". A repetitive series of different data values is used for successive radar "looks". When the sum of the added value and the previous address equals or exceeds the total number of data items for each "look", such sum has subtracted therefrom a data value corresponding to (N × M - 1) to determine the next address, where N is the number of range gates and M is the number of radar pulses for each radar "look".
Inventors
- 👤 Robert A. Conti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:03
CPC Classifications
G; G01; G01S; G01S7/00; G01S7/02; G01S7/28; G01S7/2806; G01S7/285; G01S7/292; G01S7/2923
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
290 words
In a radar system for receiving repetitively individual data items, each of which represents target information at predetermined directions and distances, each predetermined plurality of consecutively received data items constituting target information at said predetermined distances for a plurality of radar pulses during a predetermined interval, a system for rearranging the data items for each predetermined interval, comprising: means for receiving the data items for each predetermined interval representing each of the predetermined dista nces for each of the radar pulses in succession; an addressable memory address for storing each of the data items written therein in a first sequence from the receiving means during predetermined intervals; a signal processor for reading the stored data items in a predetermined second sequence different from the write-in sequence; means to select a predetermined sequence of addresses in the memory device, the total number of said selected addresses being no greater than the total number of data items of a predetermined interval, for reading out in the second sequence the data items of one predetermined interval while writing in the first sequence data items of the next predetermined interval, said address selection means including, means to add the same predetermined value N k to each preceding address of a predetermined interval write-in read-out sequence to determine the next address in such sequence; means to subtract a predetermined value corresponding to the total number of data items less one in a predetermined interval from the sum of the value N k and the preceding address at times when said sum is equal to or greater than said total number of data items to determine the next address in such sequence; and means to select a predetermined value N k for each individual predetermined interval.
Claim 2
Dependent Claim
290 words
In a radar system for receiving repetitively individual data items, each of which represents target information at predetermined directions and distances, each predetermined plurality of consecutively received data items constituting target information at said predetermined distances for a plurality of radar pulses during a predetermined interval, a system for rearranging the data items for each predetermined interval, comprising: means for receiving the data items for each predetermined interval representing each of the predetermined dista nces for each of the radar pulses in succession; an addressable memory address for storing each of the data items written therein in a first sequence from the receiving means during predetermined intervals; a signal processor for reading the stored data items in a predetermined second sequence different from the write-in sequence; means to select a predetermined sequence of addresses in the memory device, the total number of said selected addresses being no greater than the total number of data items of a predetermined interval, for reading out in the second sequence the data items of one predetermined interval while writing in the first sequence data items of the next predetermined interval, said address selection means including, means to add the same predetermined value N k to each preceding address of a predetermined interval write-in read-out sequence to determine the next address in such sequence; means to subtract a predetermined value corresponding to the total number of data items less one in a predetermined interval from the sum of the value N k and the preceding address at times when said sum is equal to or greater than said total number of data items to determine the next address in such sequence; and means to select a predetermined value N k for each individual predetermined interval.
Claim 3
Dependent Claim
40 words
In a system according to claim 1 wherein the means to select the value N k for each successive predetermined interval comprises: means to calculate a first predetermined value N k for the next predetermined interval during the preceding interval.
Claim 4
Dependent Claim
193 words
In a system according to claim 1 wherein the means to select the value N k for each successive predetermined interval comprises means to generate a first predetermined value N k during one predetermined interval to determine the N k value for a second predetermined interval; means to add the N k values for the second interval during the write-in read-out sequence of each of a predetermined number of data items during said second predetermined interval to determine the N k value for a third predetermined interval; means to detect a sum of the N k value for each of the predetermined number of data items for the second predetermined interval and the N k value of each of the predetermined number of data items for the third predetermined interval whenever such sum is at least equal to the total number of data items of each predetermined interval; and means responsive to such detection means to subtract therefrom a value corresponding to the total number of data items less one during each write-in read-out sequence of the predetermined number of data items to determine the N k value of the third predetermined interval.
Claim 5
Independent Claim
202 words
A system for repetitively rearranging the read-out sequence of the individual data items in each of a plurality of data sets different than the write-in sequence of such data items, comprising: an addressable memory device having a plurality of individual memory addresses for storing each of the data items of a data set; means to select a predetermined sequence of addresses in the memory device, the total number of selected addresses being no greater than the total number of selected addresses being no greater than the total number of data items in a data set, said address selection means including: means to add the same predetermined value N k to each preceding address of a data item of a data set to determine the next address for the data set; means to subtract a predetermined value corresponding to the total number of data items less 1 of a data set from the sum of the value N k and the preceding address at times when said sum is equal to or greater than said total number of data items to determine the next address of the same data set; and means to select a predetermined value N k for each data set.
Claim 6
Independent Claim
202 words
A system for repetitively rearranging the read-out sequence of the individual data items in each of a plurality of data sets different than the write-in sequence of such data items, comprising: an addressable memory device having a plurality of individual memory addresses for storing each of the data items of a data set; means to select a predetermined sequence of addresses in the memory device, the total number of selected addresses being no greater than the total number of selected addresses being no greater than the total number of data items in a data set, said address selection means including: means to add the same predetermined value N k to each preceding address of a data item of a data set to determine the next address for the data set; means to subtract a predetermined value corresponding to the total number of data items less 1 of a data set from the sum of the value N k and the preceding address at times when said sum is equal to or greater than said total number of data items to determine the next address of the same data set; and means to select a predetermined value N k for each data set.
Claim 7
Dependent Claim
45 words
A system according to claim 4 wherein the means to select the value N k for successive data sets comprises means to calculate a first predetermined value N k for one data set in accordance with the value N k for the preceding data set.
Claim 8
Dependent Claim
130 words
A system according to claim 4 wherein the means to select the value N k for successive data sets comprises: means to generate a first predetermined value N k during one write-in read-out sequence to determine the N k value for a second write-in read-out sequence; means to sum a predetermined number of N k values during said second sequence to determine the N k value for a third sequence; means to detect an N k value summation at least equal to the total number of data items in a data set; and means responsive to such detection means to subtract therefrom a value corresponding to the total number of data items less one for each of the selected summations to determine the N k value for the third sequence.
Claim 9
Independent Claim
118 words
A method of addressing a memory device for reading out data items constituting a data set in a predetermined sequence different from a predetermined write-in sequence of said data items where the data items of one set are being written into the same address while the data items of another data set are being read out, comprising the steps of: adding a predetermined value N k to each preceding address to determine the next address for each sequence; subtracting a predetermined value less than the total number of data items from the resulting sum of the first step at times when said sum is equal to or greater than the number of data items of a data set.
Claim 10
Independent Claim
118 words
A method of addressing a memory device for reading out data items constituting a data set in a predetermined sequence different from a predetermined write-in sequence of said data items where the data items of one set are being written into the same address while the data items of another data set are being read out, comprising the steps of: adding a predetermined value N k to each preceding address to determine the next address for each sequence; subtracting a predetermined value less than the total number of data items from the resulting sum of the first step at times when said sum is equal to or greater than the number of data items of a data set.
Claim 11
Dependent Claim
40 words
A method according to claim 7 wherein the step of subtracting a predetermined value less than the total number of data items includes the step of subtracting a predetermined value equal to the total number of data items less one.
References Cited (Backward Citations)
US3633173A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-20 | 1981-09-19 | 1982-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-20 | 1985-09-19 | 1986-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-20 | 1989-09-19 | 1990-03-21 | $7700.00 | Window Closed / Lapsed |