Data transfer system

Claim 2

A data transfer system for receiving incoming digital data serially at a predetermined bit rate and transferring said data serially at a different bit rate, said data transfer system comprising distributing means for distributing the bits of incoming data into a plurality of groups; delay means connected to the distributing means for delaying the bits of each group by predetermined delay times; assembly means connected to the distributing means and the delay means for assembling the delayed bits of each group into a group having a bit rate different from that of the incoming data; and an output coupled to the assembly means.

Claim 3

A data transfer system for receiving incoming digital data serially at a predetermined bit rate and transferring said data serially at a bit rate which is an integer times said predetermined bit rate, said data transfer system comprising distributing means for distributing the incoming data into a plurality of groups continuously, bit by bit; delay means connected to the distributing means for delaying the bits of each group by predetermined delay times; assembly means connected to the distributing means and the delay means for assembling the bits of each group into a group wherein successive bits of one group are interposed between successive bits of another group whereby the bits of the different groups alternate thereby providing a bit rate which is an integer times said predetermined bit rate; and an output coupled to the assembly means.

Claim 4

A data transfer system for receiving incoming digital data serially at a predetermined bit rate and transferring said data serially at a bit rate which is an integer times said predetermined bit rate, said data transfer system comprising distributing means for distributing the incoming data into a plurality of groups continuously, bit by bit; delay means connected to the distributing means for delaying the bits of each group by predetermined delay times; assembly means connected to the distributing means and the delay means for assembling the bits of each group into a group wherein successive bits of one group are interposed between successive bits of another group whereby the bits of the different groups alternate thereby providing a bit rate which is an integer times said predetermined bit rate; and an output coupled to the assembly means.

Claim 5

A data transfer system for receiving incoming digital data serially at a predetermined bit rate and transferring said data serially at a bit rate which is one over an integer times said predetermined bit rate, said data transfer system comprising distributing means for distributing the incoming data into a plurality of groups sequentially bit by bit; delay means connected to the distributing means for delaying the bits of each group by predetermined delay times; assembly means connected to the distributing means and the delay means for assembling the bits of each group sequentially in series thereby providing a bit rate which is one over an integer times said predetermined bit rate; and an output coupled to the assembly means.

Claim 6

A data transfer system for receiving incoming digital data serially at a predetermined bit rate and transferring said data serially at a bit rate which is one over an integer times said predetermined bit rate, said data transfer system comprising distributing means for distributing the incoming data into a plurality of groups sequentially bit by bit; delay means connected to the distributing means for delaying the bits of each group by predetermined delay times; assembly means connected to the distributing means and the delay means for assembling the bits of each group sequentially in series thereby providing a bit rate which is one over an integer times said predetermined bit rate; and an output coupled to the assembly means.

Claim 7

A data transfer system as claimed in claim 2, wherein the delay means provides zero delay for the bits of a specified group.

Claim 8

A data transfer system as claimed in claim 2, wherein the delay means comprises a shift register.

Claim 9

A data transfer system as claimed in claim 3, wherein the delay means provides zero delay for the bits of a specified group.

Claim 10

A data transfer system as claimed in claim 3, wherein the delay means comprises a shift register.

Claim 11

A data transfer system for receiving incoming digital data serially at a first predetermined bit rate, writing said incoming data on a revolving record medium at a bit rate which is an integer times said first predetermined bit rate, and transferring data read out from the revolving record medium at a second predetermined bit rate at a bit rate different from said second predetermined bit rate, said data transfer system comprising a revolving record medium comprising a magnetic disc having a surface with plurality of concentric circular areas and a plurality of sectors intersecting said circular areas to form sectoral areas; a write-in circuit having first distributing means for distributing the incoming data into a plurality of groups continuously, bit by bit, first delay means connected to the first distributing means for delaying the bits of each group by predetermined delay times, and first assembly means connected to the first distributing means and the first delay means for assembling the bits of each group into a first new group wherein successive bits of one group are interposed between successive bits of another group whereby the bits of the different groups alternate thereby providing a bit rate which is an integer times said first predetermined bit rate, writing means coupled to the first assembly means and said revolving record means for writing the data of the first new group into a plurality of selected alternate sectoral areas of the surface of said disc; and a readout circuit having second distributing means for distributing data into a plurality of groups sequentially bit by bit, second delay means connected to the second distributing means for delaying the bits of each group by predetermined delay times, second assembly means connected to the second distributing means and the second delay means for assembling the bits of each group sequentially in series thereby providing a bit rate which is one over an integer times said first predetermined bit rate, readout means in operative proximity with the disc and coupled to the second distributing means for reading the sequential series data out from selected alternate sectoral areas of the surface of said disc, and an output coupled to the second assembly means.

Claim 12

A data transfer system for receiving incoming digital data serially at a first predetermined bit rate, writing said incoming data on a revolving record medium at a bit rate which is an integer times said first predetermined bit rate, and transferring data read out from the revolving record medium at a second predetermined bit rate at a bit rate different from said second predetermined bit rate, said data transfer system comprising a revolving record medium comprising a magnetic disc having a surface with plurality of concentric circular areas and a plurality of sectors intersecting said circular areas to form sectoral areas; a write-in circuit having first distributing means for distributing the incoming data into a plurality of groups continuously, bit by bit, first delay means connected to the first distributing means for delaying the bits of each group by predetermined delay times, and first assembly means connected to the first distributing means and the first delay means for assembling the bits of each group into a first new group wherein successive bits of one group are interposed between successive bits of another group whereby the bits of the different groups alternate thereby providing a bit rate which is an integer times said first predetermined bit rate, writing means coupled to the first assembly means and said revolving record means for writing the data of the first new group into a plurality of selected alternate sectoral areas of the surface of said disc; and a readout circuit having second distributing means for distributing data into a plurality of groups sequentially bit by bit, second delay means connected to the second distributing means for delaying the bits of each group by predetermined delay times, second assembly means connected to the second distributing means and the second delay means for assembling the bits of each group sequentially in series thereby providing a bit rate which is one over an integer times said first predetermined bit rate, readout means in operative proximity with the disc and coupled to the second distributing means for reading the sequential series data out from selected alternate sectoral areas of the surface of said disc, and an output coupled to the second assembly means.