US4482907A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Planar-type field-effect transistor having metallized-well electrodes and a method of fabrication of said transistor
Assignee: Thales SA
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Filing: 1982-03-08
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Granted: 1984-11-13
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Expires: 2002-03-08
Abstract
Abstract A field-effect transistor having a gate consisting of a metallic plane projecting metallized wells of less than one micron in diameter through the channel layer downwards to the semiconductor substrate. They are formed by ion-beam etching. Metallization is performed by cathodic sputtering of a substance which forms a Schottky contact with the semiconductor. The wells are spaced at intervals of less than one micron so as to form a row and are joined together by means of a gate electrode.
Inventors
- 👤 Paul R. Jay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:04
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0618; H10D30/80; H10D30/87; H10D30/873; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/256; H10D64/27; H10D64/311; H10D64/411; H10W; H10W20/00; H10W20/01; H10W20/021; H10W20/20
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
90 words
A planar field-effect transistor comprising: a semiconductor substrate; an active semiconductor layer arranged on said substrate; a source electrode located on said active layer; a drain electrode located on said active layer; at least one gate electrode having a first portion arranged on said active layer and a second portion formed as a plurality of metallized wells arranged in a row in a plane normal to the direction of the drainsource current, each of said wells extending downwardly from said first portion through said active layer and into said substrate.
Claim 2
Dependent Claim
90 words
A planar field-effect transistor comprising: a semiconductor substrate; an active semiconductor layer arranged on said substrate; a source electrode located on said active layer; a drain electrode located on said active layer; at least one gate electrode having a first portion arranged on said active layer and a second portion formed as a plurality of metallized wells arranged in a row in a plane normal to the direction of the drainsource current, each of said wells extending downwardly from said first portion through said active layer and into said substrate.
Claim 3
Dependent Claim
21 words
A transistor according to claim 1, wherein said source electrode and said drain electrode each extend downwardly into said active layer.
Claim 4
Dependent Claim
17 words
A transistor according to claims 1 or 2 wherein said transistor comprises at least two gate electrodes.
Claim 5
Dependent Claim
22 words
A transistor according to claim 3 wherein the interval between wells is different for each of said at least two gate electrodes.
Claim 6
Dependent Claim
23 words
A transistor according to claim 3 wherein each of said gate electrodes is offset from the others in the direction of said row.
Claim 7
Dependent Claim
73 words
A transistor according to claim 1 wherein a free region is formed in said active layer and said substrate around each of said gate electrodes when a potential is applied thereto, the regions in the substate touching each other to form a single continuous region while the regions in the active layer do not touch, so that the charge-carrier conduction region is limited to the space between the wells in the active layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-11-13 | 1988-05-14 | 1988-11-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-11-13 | 1992-05-14 | 1992-11-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-11-13 | 1996-05-14 | 1996-11-13 | $7700.00 | Window Closed / Lapsed |